git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 8faf3b317471179c02db339aa80955a2e88c036d Mon Sep 17 00:00:00 2001
   2 From: Zhao Yakui <yakui.zhao@intel.com>
   3 Date: Mon, 4 Jan 2010 16:29:31 +0800
   4 Subject: drm/i915: Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake
   5
   6 From: Zhao Yakui <yakui.zhao@intel.com>
   7
   8 commit 8faf3b317471179c02db339aa80955a2e88c036d upstream.
   9
  10 Make the BPC in FDI rx/transcoder be consistent with that in pipeconf on Ironlake.
  11
  12 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
  13 Signed-off-by: Eric Anholt <eric@anholt.net>
  14 Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
  15
  16 ---
  17  drivers/gpu/drm/i915/intel_display.c |   26 +++++++++++++++++++++++++-
  18  1 file changed, 25 insertions(+), 1 deletion(-)
  19
  20 --- a/drivers/gpu/drm/i915/intel_display.c
  21 +++ b/drivers/gpu/drm/i915/intel_display.c
  22 @@ -1473,6 +1473,10 @@ static void igdng_crtc_dpms(struct drm_c
  23         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
  24         u32 temp;
  25         int tries = 5, j, n;
  26 +       u32 pipe_bpc;
  27 +
  28 +       temp = I915_READ(pipeconf_reg);
  29 +       pipe_bpc = temp & PIPE_BPC_MASK;
  30
  31         /* XXX: When our outputs are all unaware of DPMS modes other than off
  32          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  33 @@ -1504,6 +1508,12 @@ static void igdng_crtc_dpms(struct drm_c
  34
  35                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  36                         temp = I915_READ(fdi_rx_reg);
  37 +                       /*
  38 +                        * make the BPC in FDI Rx be consistent with that in
  39 +                        * pipeconf reg.
  40 +                        */
  41 +                       temp &= ~(0x7 << 16);
  42 +                       temp |= (pipe_bpc << 11);
  43                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
  44                                         FDI_SEL_PCDCLK |
  45                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
  46 @@ -1644,6 +1654,12 @@ static void igdng_crtc_dpms(struct drm_c
  47
  48                         /* enable PCH transcoder */
  49                         temp = I915_READ(transconf_reg);
  50 +                       /*
  51 +                        * make the BPC in transcoder be consistent with
  52 +                        * that in pipeconf reg.
  53 +                        */
  54 +                       temp &= ~PIPE_BPC_MASK;
  55 +                       temp |= pipe_bpc;
  56                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
  57                         I915_READ(transconf_reg);
  58
  59 @@ -1722,6 +1738,9 @@ static void igdng_crtc_dpms(struct drm_c
  60                 I915_READ(fdi_tx_reg);
  61
  62                 temp = I915_READ(fdi_rx_reg);
  63 +               /* BPC in FDI rx is consistent with that in pipeconf */
  64 +               temp &= ~(0x07 << 16);
  65 +               temp |= (pipe_bpc << 11);
  66                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
  67                 I915_READ(fdi_rx_reg);
  68
  69 @@ -1765,7 +1784,12 @@ static void igdng_crtc_dpms(struct drm_c
  70                                 }
  71                         }
  72                 }
  73 -
  74 +               temp = I915_READ(transconf_reg);
  75 +               /* BPC in transcoder is consistent with that in pipeconf */
  76 +               temp &= ~PIPE_BPC_MASK;
  77 +               temp |= pipe_bpc;
  78 +               I915_WRITE(transconf_reg, temp);
  79 +               I915_READ(transconf_reg);
  80                 udelay(100);
  81
  82                 /* disable PCH DPLL */