git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 75d1cc0e05af579301ce4e49cf6399be4b4e6e76 Mon Sep 17 00:00:00 2001
   2 From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
   3 Date: Thu, 17 Sep 2020 21:20:37 +0000
   4 Subject: x86/mm/pat: Don't flush cache if hardware enforces cache coherency across encryption domnains
   5
   6 From: Krish Sadhukhan <krish.sadhukhan@oracle.com>
   7
   8 commit 75d1cc0e05af579301ce4e49cf6399be4b4e6e76 upstream.
   9
  10 In some hardware implementations, coherency between the encrypted and
  11 unencrypted mappings of the same physical page is enforced. In such a
  12 system, it is not required for software to flush the page from all CPU
  13 caches in the system prior to changing the value of the C-bit for the
  14 page. So check that bit before flushing the cache.
  15
  16  [ bp: Massage commit message. ]
  17
  18 Suggested-by: Tom Lendacky <thomas.lendacky@amd.com>
  19 Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
  20 Signed-off-by: Borislav Petkov <bp@suse.de>
  21 Link: https://lkml.kernel.org/r/20200917212038.5090-3-krish.sadhukhan@oracle.com
  22 Signed-off-by: Liam Merwick <liam.merwick@oracle.com>
  23 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  24 ---
  25  arch/x86/mm/pageattr.c |    2 +-
  26  1 file changed, 1 insertion(+), 1 deletion(-)
  27
  28 --- a/arch/x86/mm/pageattr.c
  29 +++ b/arch/x86/mm/pageattr.c
  30 @@ -1967,7 +1967,7 @@ static int __set_memory_enc_dec(unsigned
  31         /*
  32          * Before changing the encryption attribute, we need to flush caches.
  33          */
  34 -       cpa_flush(&cpa, 1);
  35 +       cpa_flush(&cpa, !this_cpu_has(X86_FEATURE_SME_COHERENT));
  36
  37         ret = __change_page_attr_set_clr(&cpa, 1);
  38