]> git.ipfire.org Git - thirdparty/openwrt.git/blob
projects / thirdparty / openwrt.git / blob
? search:


db4494e12f2a9a5f76688ded7964d81b60f9a044
[thirdparty/openwrt.git] /
1 From f252493e1835366fc25ce631c3056f900977dd11 Mon Sep 17 00:00:00 2001
2 From: Lorenzo Bianconi <lorenzo@kernel.org>
3 Date: Fri, 18 Apr 2025 12:40:50 +0200
4 Subject: [PATCH 2/2] net: airoha: Enable multiple IRQ lines support in
5 airoha_eth driver.
6
7 EN7581 ethernet SoC supports 4 programmable IRQ lines for Tx and Rx
8 interrupts. Enable multiple IRQ lines support. Map Rx/Tx queues to the
9 available IRQ lines using the default scheme used in the vendor SDK:
10
11 - IRQ0: rx queues [0-4],[7-9],15
12 - IRQ1: rx queues [21-30]
13 - IRQ2: rx queues 5
14 - IRQ3: rx queues 6
15
16 Tx queues interrupts are managed by IRQ0.
17
18 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
19 Link: https://patch.msgid.link/20250418-airoha-eth-multi-irq-v1-2-1ab0083ca3c1@kernel.org
20 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
21 ---
22 drivers/net/ethernet/airoha/airoha_eth.c | 67 +++++---
23 drivers/net/ethernet/airoha/airoha_eth.h | 13 +-
24 drivers/net/ethernet/airoha/airoha_regs.h | 185 +++++++++++++++++-----
25 3 files changed, 206 insertions(+), 59 deletions(-)
26
27 --- a/drivers/net/ethernet/airoha/airoha_eth.c
28 +++ b/drivers/net/ethernet/airoha/airoha_eth.c
29 @@ -735,7 +735,6 @@ free_frag:
30 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget)
31 {
32 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi);
33 - struct airoha_irq_bank *irq_bank = &q->qdma->irq_banks[0];
34 int cur, done = 0;
35
36 do {
37 @@ -743,9 +742,20 @@ static int airoha_qdma_rx_napi_poll(stru
38 done += cur;
39 } while (cur && done < budget);
40
41 - if (done < budget && napi_complete(napi))
42 - airoha_qdma_irq_enable(irq_bank, QDMA_INT_REG_IDX1,
43 - RX_DONE_INT_MASK);
44 + if (done < budget && napi_complete(napi)) {
45 + struct airoha_qdma *qdma = q->qdma;
46 + int i, qid = q - &qdma->q_rx[0];
47 + int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1
48 + : QDMA_INT_REG_IDX2;
49 +
50 + for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
51 + if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i)))
52 + continue;
53 +
54 + airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg,
55 + BIT(qid % RX_DONE_HIGH_OFFSET));
56 + }
57 + }
58
59 return done;
60 }
61 @@ -1179,17 +1189,24 @@ static int airoha_qdma_hw_init(struct ai
62 {
63 int i;
64
65 - /* clear pending irqs */
66 - for (i = 0; i < ARRAY_SIZE(qdma->irq_banks[0].irqmask); i++)
67 + for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) {
68 + /* clear pending irqs */
69 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff);
70 -
71 - /* setup irqs */
72 + /* setup rx irqs */
73 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0,
74 + INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i)));
75 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1,
76 + INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i)));
77 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2,
78 + INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i)));
79 + airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3,
80 + INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i)));
81 + }
82 + /* setup tx irqs */
83 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0,
84 - INT_IDX0_MASK);
85 - airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX1,
86 - INT_IDX1_MASK);
87 + TX_COHERENT_LOW_INT_MASK | INT_TX_MASK);
88 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4,
89 - INT_IDX4_MASK);
90 + TX_COHERENT_HIGH_INT_MASK);
91
92 /* setup irq binding */
93 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
94 @@ -1236,6 +1253,7 @@ static irqreturn_t airoha_irq_handler(in
95 {
96 struct airoha_irq_bank *irq_bank = dev_instance;
97 struct airoha_qdma *qdma = irq_bank->qdma;
98 + u32 rx_intr_mask = 0, rx_intr1, rx_intr2;
99 u32 intr[ARRAY_SIZE(irq_bank->irqmask)];
100 int i;
101
102 @@ -1248,17 +1266,24 @@ static irqreturn_t airoha_irq_handler(in
103 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state))
104 return IRQ_NONE;
105
106 - if (intr[1] & RX_DONE_INT_MASK) {
107 - airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1,
108 - RX_DONE_INT_MASK);
109 + rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK;
110 + if (rx_intr1) {
111 + airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1);
112 + rx_intr_mask |= rx_intr1;
113 + }
114
115 - for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) {
116 - if (!qdma->q_rx[i].ndesc)
117 - continue;
118 + rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK;
119 + if (rx_intr2) {
120 + airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2);
121 + rx_intr_mask |= (rx_intr2 << 16);
122 + }
123
124 - if (intr[1] & BIT(i))
125 - napi_schedule(&qdma->q_rx[i].napi);
126 - }
127 + for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) {
128 + if (!qdma->q_rx[i].ndesc)
129 + continue;
130 +
131 + if (rx_intr_mask & BIT(i))
132 + napi_schedule(&qdma->q_rx[i].napi);
133 }
134
135 if (intr[0] & INT_TX_MASK) {
136 --- a/drivers/net/ethernet/airoha/airoha_eth.h
137 +++ b/drivers/net/ethernet/airoha/airoha_eth.h
138 @@ -17,7 +17,7 @@
139
140 #define AIROHA_MAX_NUM_GDM_PORTS 4
141 #define AIROHA_MAX_NUM_QDMA 2
142 -#define AIROHA_MAX_NUM_IRQ_BANKS 1
143 +#define AIROHA_MAX_NUM_IRQ_BANKS 4
144 #define AIROHA_MAX_DSA_PORTS 7
145 #define AIROHA_MAX_NUM_RSTS 3
146 #define AIROHA_MAX_NUM_XSI_RSTS 5
147 @@ -453,6 +453,17 @@ struct airoha_flow_table_entry {
148 unsigned long cookie;
149 };
150
151 +/* RX queue to IRQ mapping: BIT(q) in IRQ(n) */
152 +#define RX_IRQ0_BANK_PIN_MASK 0x839f
153 +#define RX_IRQ1_BANK_PIN_MASK 0x7fe00000
154 +#define RX_IRQ2_BANK_PIN_MASK 0x20
155 +#define RX_IRQ3_BANK_PIN_MASK 0x40
156 +#define RX_IRQ_BANK_PIN_MASK(_n) \
157 + (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \
158 + ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \
159 + ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \
160 + RX_IRQ0_BANK_PIN_MASK)
161 +
162 struct airoha_irq_bank {
163 struct airoha_qdma *qdma;
164
165 --- a/drivers/net/ethernet/airoha/airoha_regs.h
166 +++ b/drivers/net/ethernet/airoha/airoha_regs.h
167 @@ -463,6 +463,26 @@
168 #define IRQ0_FULL_INT_MASK BIT(1)
169 #define IRQ0_INT_MASK BIT(0)
170
171 +#define RX_COHERENT_LOW_INT_MASK \
172 + (RX15_COHERENT_INT_MASK | RX14_COHERENT_INT_MASK | \
173 + RX13_COHERENT_INT_MASK | RX12_COHERENT_INT_MASK | \
174 + RX11_COHERENT_INT_MASK | RX10_COHERENT_INT_MASK | \
175 + RX9_COHERENT_INT_MASK | RX8_COHERENT_INT_MASK | \
176 + RX7_COHERENT_INT_MASK | RX6_COHERENT_INT_MASK | \
177 + RX5_COHERENT_INT_MASK | RX4_COHERENT_INT_MASK | \
178 + RX3_COHERENT_INT_MASK | RX2_COHERENT_INT_MASK | \
179 + RX1_COHERENT_INT_MASK | RX0_COHERENT_INT_MASK)
180 +
181 +#define RX_COHERENT_LOW_OFFSET __ffs(RX_COHERENT_LOW_INT_MASK)
182 +#define INT_RX0_MASK(_n) \
183 + (((_n) << RX_COHERENT_LOW_OFFSET) & RX_COHERENT_LOW_INT_MASK)
184 +
185 +#define TX_COHERENT_LOW_INT_MASK \
186 + (TX7_COHERENT_INT_MASK | TX6_COHERENT_INT_MASK | \
187 + TX5_COHERENT_INT_MASK | TX4_COHERENT_INT_MASK | \
188 + TX3_COHERENT_INT_MASK | TX2_COHERENT_INT_MASK | \
189 + TX1_COHERENT_INT_MASK | TX0_COHERENT_INT_MASK)
190 +
191 #define TX_DONE_INT_MASK(_n) \
192 ((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK \
193 : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
194 @@ -471,17 +491,6 @@
195 (IRQ1_INT_MASK | IRQ1_FULL_INT_MASK | \
196 IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
197
198 -#define INT_IDX0_MASK \
199 - (TX0_COHERENT_INT_MASK | TX1_COHERENT_INT_MASK | \
200 - TX2_COHERENT_INT_MASK | TX3_COHERENT_INT_MASK | \
201 - TX4_COHERENT_INT_MASK | TX5_COHERENT_INT_MASK | \
202 - TX6_COHERENT_INT_MASK | TX7_COHERENT_INT_MASK | \
203 - RX0_COHERENT_INT_MASK | RX1_COHERENT_INT_MASK | \
204 - RX2_COHERENT_INT_MASK | RX3_COHERENT_INT_MASK | \
205 - RX4_COHERENT_INT_MASK | RX7_COHERENT_INT_MASK | \
206 - RX8_COHERENT_INT_MASK | RX9_COHERENT_INT_MASK | \
207 - RX15_COHERENT_INT_MASK | INT_TX_MASK)
208 -
209 /* QDMA_CSR_INT_ENABLE2 */
210 #define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
211 #define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
212 @@ -516,19 +525,121 @@
213 #define RX1_DONE_INT_MASK BIT(1)
214 #define RX0_DONE_INT_MASK BIT(0)
215
216 -#define RX_DONE_INT_MASK \
217 - (RX0_DONE_INT_MASK | RX1_DONE_INT_MASK | \
218 - RX2_DONE_INT_MASK | RX3_DONE_INT_MASK | \
219 - RX4_DONE_INT_MASK | RX7_DONE_INT_MASK | \
220 - RX8_DONE_INT_MASK | RX9_DONE_INT_MASK | \
221 - RX15_DONE_INT_MASK)
222 -#define INT_IDX1_MASK \
223 - (RX_DONE_INT_MASK | \
224 - RX0_NO_CPU_DSCP_INT_MASK | RX1_NO_CPU_DSCP_INT_MASK | \
225 - RX2_NO_CPU_DSCP_INT_MASK | RX3_NO_CPU_DSCP_INT_MASK | \
226 - RX4_NO_CPU_DSCP_INT_MASK | RX7_NO_CPU_DSCP_INT_MASK | \
227 - RX8_NO_CPU_DSCP_INT_MASK | RX9_NO_CPU_DSCP_INT_MASK | \
228 - RX15_NO_CPU_DSCP_INT_MASK)
229 +#define RX_NO_CPU_DSCP_LOW_INT_MASK \
230 + (RX15_NO_CPU_DSCP_INT_MASK | RX14_NO_CPU_DSCP_INT_MASK | \
231 + RX13_NO_CPU_DSCP_INT_MASK | RX12_NO_CPU_DSCP_INT_MASK | \
232 + RX11_NO_CPU_DSCP_INT_MASK | RX10_NO_CPU_DSCP_INT_MASK | \
233 + RX9_NO_CPU_DSCP_INT_MASK | RX8_NO_CPU_DSCP_INT_MASK | \
234 + RX7_NO_CPU_DSCP_INT_MASK | RX6_NO_CPU_DSCP_INT_MASK | \
235 + RX5_NO_CPU_DSCP_INT_MASK | RX4_NO_CPU_DSCP_INT_MASK | \
236 + RX3_NO_CPU_DSCP_INT_MASK | RX2_NO_CPU_DSCP_INT_MASK | \
237 + RX1_NO_CPU_DSCP_INT_MASK | RX0_NO_CPU_DSCP_INT_MASK)
238 +
239 +#define RX_DONE_LOW_INT_MASK \
240 + (RX15_DONE_INT_MASK | RX14_DONE_INT_MASK | \
241 + RX13_DONE_INT_MASK | RX12_DONE_INT_MASK | \
242 + RX11_DONE_INT_MASK | RX10_DONE_INT_MASK | \
243 + RX9_DONE_INT_MASK | RX8_DONE_INT_MASK | \
244 + RX7_DONE_INT_MASK | RX6_DONE_INT_MASK | \
245 + RX5_DONE_INT_MASK | RX4_DONE_INT_MASK | \
246 + RX3_DONE_INT_MASK | RX2_DONE_INT_MASK | \
247 + RX1_DONE_INT_MASK | RX0_DONE_INT_MASK)
248 +
249 +#define RX_NO_CPU_DSCP_LOW_OFFSET __ffs(RX_NO_CPU_DSCP_LOW_INT_MASK)
250 +#define INT_RX1_MASK(_n) \
251 + ((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) | \
252 + (RX_DONE_LOW_INT_MASK & (_n)))
253 +
254 +/* QDMA_CSR_INT_ENABLE3 */
255 +#define RX31_NO_CPU_DSCP_INT_MASK BIT(31)
256 +#define RX30_NO_CPU_DSCP_INT_MASK BIT(30)
257 +#define RX29_NO_CPU_DSCP_INT_MASK BIT(29)
258 +#define RX28_NO_CPU_DSCP_INT_MASK BIT(28)
259 +#define RX27_NO_CPU_DSCP_INT_MASK BIT(27)
260 +#define RX26_NO_CPU_DSCP_INT_MASK BIT(26)
261 +#define RX25_NO_CPU_DSCP_INT_MASK BIT(25)
262 +#define RX24_NO_CPU_DSCP_INT_MASK BIT(24)
263 +#define RX23_NO_CPU_DSCP_INT_MASK BIT(23)
264 +#define RX22_NO_CPU_DSCP_INT_MASK BIT(22)
265 +#define RX21_NO_CPU_DSCP_INT_MASK BIT(21)
266 +#define RX20_NO_CPU_DSCP_INT_MASK BIT(20)
267 +#define RX19_NO_CPU_DSCP_INT_MASK BIT(19)
268 +#define RX18_NO_CPU_DSCP_INT_MASK BIT(18)
269 +#define RX17_NO_CPU_DSCP_INT_MASK BIT(17)
270 +#define RX16_NO_CPU_DSCP_INT_MASK BIT(16)
271 +#define RX31_DONE_INT_MASK BIT(15)
272 +#define RX30_DONE_INT_MASK BIT(14)
273 +#define RX29_DONE_INT_MASK BIT(13)
274 +#define RX28_DONE_INT_MASK BIT(12)
275 +#define RX27_DONE_INT_MASK BIT(11)
276 +#define RX26_DONE_INT_MASK BIT(10)
277 +#define RX25_DONE_INT_MASK BIT(9)
278 +#define RX24_DONE_INT_MASK BIT(8)
279 +#define RX23_DONE_INT_MASK BIT(7)
280 +#define RX22_DONE_INT_MASK BIT(6)
281 +#define RX21_DONE_INT_MASK BIT(5)
282 +#define RX20_DONE_INT_MASK BIT(4)
283 +#define RX19_DONE_INT_MASK BIT(3)
284 +#define RX18_DONE_INT_MASK BIT(2)
285 +#define RX17_DONE_INT_MASK BIT(1)
286 +#define RX16_DONE_INT_MASK BIT(0)
287 +
288 +#define RX_NO_CPU_DSCP_HIGH_INT_MASK \
289 + (RX31_NO_CPU_DSCP_INT_MASK | RX30_NO_CPU_DSCP_INT_MASK | \
290 + RX29_NO_CPU_DSCP_INT_MASK | RX28_NO_CPU_DSCP_INT_MASK | \
291 + RX27_NO_CPU_DSCP_INT_MASK | RX26_NO_CPU_DSCP_INT_MASK | \
292 + RX25_NO_CPU_DSCP_INT_MASK | RX24_NO_CPU_DSCP_INT_MASK | \
293 + RX23_NO_CPU_DSCP_INT_MASK | RX22_NO_CPU_DSCP_INT_MASK | \
294 + RX21_NO_CPU_DSCP_INT_MASK | RX20_NO_CPU_DSCP_INT_MASK | \
295 + RX19_NO_CPU_DSCP_INT_MASK | RX18_NO_CPU_DSCP_INT_MASK | \
296 + RX17_NO_CPU_DSCP_INT_MASK | RX16_NO_CPU_DSCP_INT_MASK)
297 +
298 +#define RX_DONE_HIGH_INT_MASK \
299 + (RX31_DONE_INT_MASK | RX30_DONE_INT_MASK | \
300 + RX29_DONE_INT_MASK | RX28_DONE_INT_MASK | \
301 + RX27_DONE_INT_MASK | RX26_DONE_INT_MASK | \
302 + RX25_DONE_INT_MASK | RX24_DONE_INT_MASK | \
303 + RX23_DONE_INT_MASK | RX22_DONE_INT_MASK | \
304 + RX21_DONE_INT_MASK | RX20_DONE_INT_MASK | \
305 + RX19_DONE_INT_MASK | RX18_DONE_INT_MASK | \
306 + RX17_DONE_INT_MASK | RX16_DONE_INT_MASK)
307 +
308 +#define RX_DONE_INT_MASK (RX_DONE_HIGH_INT_MASK | RX_DONE_LOW_INT_MASK)
309 +#define RX_DONE_HIGH_OFFSET fls(RX_DONE_HIGH_INT_MASK)
310 +
311 +#define INT_RX2_MASK(_n) \
312 + ((RX_NO_CPU_DSCP_HIGH_INT_MASK & (_n)) | \
313 + (((_n) >> RX_DONE_HIGH_OFFSET) & RX_DONE_HIGH_INT_MASK))
314 +
315 +/* QDMA_CSR_INT_ENABLE4 */
316 +#define RX31_COHERENT_INT_MASK BIT(31)
317 +#define RX30_COHERENT_INT_MASK BIT(30)
318 +#define RX29_COHERENT_INT_MASK BIT(29)
319 +#define RX28_COHERENT_INT_MASK BIT(28)
320 +#define RX27_COHERENT_INT_MASK BIT(27)
321 +#define RX26_COHERENT_INT_MASK BIT(26)
322 +#define RX25_COHERENT_INT_MASK BIT(25)
323 +#define RX24_COHERENT_INT_MASK BIT(24)
324 +#define RX23_COHERENT_INT_MASK BIT(23)
325 +#define RX22_COHERENT_INT_MASK BIT(22)
326 +#define RX21_COHERENT_INT_MASK BIT(21)
327 +#define RX20_COHERENT_INT_MASK BIT(20)
328 +#define RX19_COHERENT_INT_MASK BIT(19)
329 +#define RX18_COHERENT_INT_MASK BIT(18)
330 +#define RX17_COHERENT_INT_MASK BIT(17)
331 +#define RX16_COHERENT_INT_MASK BIT(16)
332 +
333 +#define RX_COHERENT_HIGH_INT_MASK \
334 + (RX31_COHERENT_INT_MASK | RX30_COHERENT_INT_MASK | \
335 + RX29_COHERENT_INT_MASK | RX28_COHERENT_INT_MASK | \
336 + RX27_COHERENT_INT_MASK | RX26_COHERENT_INT_MASK | \
337 + RX25_COHERENT_INT_MASK | RX24_COHERENT_INT_MASK | \
338 + RX23_COHERENT_INT_MASK | RX22_COHERENT_INT_MASK | \
339 + RX21_COHERENT_INT_MASK | RX20_COHERENT_INT_MASK | \
340 + RX19_COHERENT_INT_MASK | RX18_COHERENT_INT_MASK | \
341 + RX17_COHERENT_INT_MASK | RX16_COHERENT_INT_MASK)
342 +
343 +#define INT_RX3_MASK(_n) (RX_COHERENT_HIGH_INT_MASK & (_n))
344
345 /* QDMA_CSR_INT_ENABLE5 */
346 #define TX31_COHERENT_INT_MASK BIT(31)
347 @@ -556,19 +667,19 @@
348 #define TX9_COHERENT_INT_MASK BIT(9)
349 #define TX8_COHERENT_INT_MASK BIT(8)
350
351 -#define INT_IDX4_MASK \
352 - (TX8_COHERENT_INT_MASK | TX9_COHERENT_INT_MASK | \
353 - TX10_COHERENT_INT_MASK | TX11_COHERENT_INT_MASK | \
354 - TX12_COHERENT_INT_MASK | TX13_COHERENT_INT_MASK | \
355 - TX14_COHERENT_INT_MASK | TX15_COHERENT_INT_MASK | \
356 - TX16_COHERENT_INT_MASK | TX17_COHERENT_INT_MASK | \
357 - TX18_COHERENT_INT_MASK | TX19_COHERENT_INT_MASK | \
358 - TX20_COHERENT_INT_MASK | TX21_COHERENT_INT_MASK | \
359 - TX22_COHERENT_INT_MASK | TX23_COHERENT_INT_MASK | \
360 - TX24_COHERENT_INT_MASK | TX25_COHERENT_INT_MASK | \
361 - TX26_COHERENT_INT_MASK | TX27_COHERENT_INT_MASK | \
362 - TX28_COHERENT_INT_MASK | TX29_COHERENT_INT_MASK | \
363 - TX30_COHERENT_INT_MASK | TX31_COHERENT_INT_MASK)
364 +#define TX_COHERENT_HIGH_INT_MASK \
365 + (TX31_COHERENT_INT_MASK | TX30_COHERENT_INT_MASK | \
366 + TX29_COHERENT_INT_MASK | TX28_COHERENT_INT_MASK | \
367 + TX27_COHERENT_INT_MASK | TX26_COHERENT_INT_MASK | \
368 + TX25_COHERENT_INT_MASK | TX24_COHERENT_INT_MASK | \
369 + TX23_COHERENT_INT_MASK | TX22_COHERENT_INT_MASK | \
370 + TX21_COHERENT_INT_MASK | TX20_COHERENT_INT_MASK | \
371 + TX19_COHERENT_INT_MASK | TX18_COHERENT_INT_MASK | \
372 + TX17_COHERENT_INT_MASK | TX16_COHERENT_INT_MASK | \
373 + TX15_COHERENT_INT_MASK | TX14_COHERENT_INT_MASK | \
374 + TX13_COHERENT_INT_MASK | TX12_COHERENT_INT_MASK | \
375 + TX11_COHERENT_INT_MASK | TX10_COHERENT_INT_MASK | \
376 + TX9_COHERENT_INT_MASK | TX8_COHERENT_INT_MASK)
377
378 #define REG_TX_IRQ_BASE(_n) ((_n) ? 0x0048 : 0x0050)
379
Mirror of https://github.com/openwrt/openwrt.git