git.ipfire.org Git - thirdparty/kernel/stable-queue.git/blob

   1 From 4428ddea832cfdb63e476eb2e5c8feb5d36057fe Mon Sep 17 00:00:00 2001
   2 From: Archana Patni <archana.patni@intel.com>
   3 Date: Wed, 23 Jul 2025 19:58:49 +0300
   4 Subject: scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers
   5
   6 From: Archana Patni <archana.patni@intel.com>
   7
   8 commit 4428ddea832cfdb63e476eb2e5c8feb5d36057fe upstream.
   9
  10 UFSHCD core disables the UIC completion interrupt when issuing UIC
  11 hibernation commands, and re-enables it afterwards if it was enabled to
  12 start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host
  13 controllers, accessing the register to re-enable the interrupt disrupts
  14 the state transition.
  15
  16 Use hibern8_notify variant operation to disable the interrupt during the
  17 entire hibernation, thereby preventing the disruption.
  18
  19 Fixes: 4049f7acef3e ("scsi: ufs: ufs-pci: Add support for Intel MTL")
  20 Cc: stable@vger.kernel.org
  21 Signed-off-by: Archana Patni <archana.patni@intel.com>
  22 Link: https://lore.kernel.org/r/20250723165856.145750-2-adrian.hunter@intel.com
  23 Reviewed-by: Bart Van Assche <bvanassche@acm.org>
  24 Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
  25 Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
  26 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  27 ---
  28  drivers/scsi/ufs/ufshcd-pci.c |   27 +++++++++++++++++++++++++++
  29  1 file changed, 27 insertions(+)
  30
  31 --- a/drivers/scsi/ufs/ufshcd-pci.c
  32 +++ b/drivers/scsi/ufs/ufshcd-pci.c
  33 @@ -203,6 +203,32 @@ out:
  34         return ret;
  35  }
  36
  37 +static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
  38 +{
  39 +       u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  40 +
  41 +       if (enable)
  42 +               set |= UIC_COMMAND_COMPL;
  43 +       else
  44 +               set &= ~UIC_COMMAND_COMPL;
  45 +       ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  46 +}
  47 +
  48 +static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba,
  49 +                                   enum uic_cmd_dme cmd,
  50 +                                   enum ufs_notify_change_status status)
  51 +{
  52 +       /*
  53 +        * Disable UIC COMPL INTR to prevent access to UFSHCI after
  54 +        * checking HCS.UPMCRS
  55 +        */
  56 +       if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER)
  57 +               ufs_intel_ctrl_uic_compl(hba, false);
  58 +
  59 +       if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT)
  60 +               ufs_intel_ctrl_uic_compl(hba, true);
  61 +}
  62 +
  63  #define INTEL_ACTIVELTR                0x804
  64  #define INTEL_IDLELTR          0x808
  65
  66 @@ -476,6 +502,7 @@ static struct ufs_hba_variant_ops ufs_in
  67         .init                   = ufs_intel_mtl_init,
  68         .exit                   = ufs_intel_common_exit,
  69         .hce_enable_notify      = ufs_intel_hce_enable_notify,
  70 +       .hibern8_notify         = ufs_intel_mtl_h8_notify,
  71         .link_startup_notify    = ufs_intel_link_startup_notify,
  72         .resume                 = ufs_intel_resume,
  73         .device_reset           = ufs_intel_device_reset,