Makefile: Add support of CONFIG_SPL_FSL_PBL

[people/ms/u-boot.git] / README

diff --git a/README b/README
index 4715cfbc2543af61ee3dc268ee3e1760eb68a394..49dcd37a3c859484247e764b3a8551b9f6bfc787 100644 (file)
--- a/README
+++ b/README
@@ -431,6 +431,10 @@ The following options need to be configured:
                This CONFIG is defined when the CPC is configured as SRAM at the
                time of U-boot entry and is required to be re-initialized.
 
                This CONFIG is defined when the CPC is configured as SRAM at the
                time of U-boot entry and is required to be re-initialized.
 

+               CONFIG_DEEP_SLEEP
+               Inidcates this SoC supports deep sleep feature. If deep sleep is
+               supported, core will start to execute uboot when wakes up.
+

 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 


@@ -458,6 +462,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 

+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+

                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 


@@ -473,7 +480,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with

-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.

 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian


@@ -490,6 +505,10 @@ The following options need to be configured:
                PBI commands can be used to configure SoC before it starts the execution.
                Please refer doc/README.pblimage for more details
 
                PBI commands can be used to configure SoC before it starts the execution.
                Please refer doc/README.pblimage for more details
 

+               CONFIG_SPL_FSL_PBL
+               It adds a target to create boot binary having SPL binary in PBI format
+               concatenated with u-boot binary.
+

                CONFIG_SYS_FSL_DDR_BE
                Defines the DDR controller register space as Big Endian
 
                CONFIG_SYS_FSL_DDR_BE
                Defines the DDR controller register space as Big Endian
 


@@ -3317,6 +3336,9 @@ FIT uImage format:
                continuing (the hardware starts execution after just
                loading the first page rather than the full 4K).
 
                continuing (the hardware starts execution after just
                loading the first page rather than the full 4K).
 

+               CONFIG_SPL_SKIP_RELOCATE
+               Avoid SPL relocation
+

                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.
                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.


@@ -4502,8 +4524,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 

-- CONFIG_SYS_QE_FMAN_FW_ADDR
-       The address in the storage device where the firmware is located.  The
+- CONFIG_SYS_FMAN_FW_ADDR
+       The address in the storage device where the FMAN microcode is located.  The
+       meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+       is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+       The address in the storage device where the QE microcode is located.  The

        meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
        is also specified.
 
        meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
        is also specified.