+
+/* Return non-zero if the architecture described by GDBARCH has
+ floating-point registers (f0 --- f31 and fpscr). */
+int
+ppc_floating_point_unit_p (struct gdbarch *gdbarch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+
+ return (tdep->ppc_fp0_regnum >= 0
+ && tdep->ppc_fpscr_regnum >= 0);
+}
+
+
+/* Check that TABLE[GDB_REGNO] is not already initialized, and then
+ set it to SIM_REGNO.
+
+ This is a helper function for init_sim_regno_table, constructing
+ the table mapping GDB register numbers to sim register numbers; we
+ initialize every element in that table to -1 before we start
+ filling it in. */
+static void
+set_sim_regno (int *table, int gdb_regno, int sim_regno)
+{
+ /* Make sure we don't try to assign any given GDB register a sim
+ register number more than once. */
+ gdb_assert (table[gdb_regno] == -1);
+ table[gdb_regno] = sim_regno;
+}
+
+
+/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
+ numbers to simulator register numbers, based on the values placed
+ in the ARCH->tdep->ppc_foo_regnum members. */
+static void
+init_sim_regno_table (struct gdbarch *arch)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+ int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
+ const struct reg *regs = tdep->regs;
+ int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
+ int i;
+
+ /* Presume that all registers not explicitly mentioned below are
+ unavailable from the sim. */
+ for (i = 0; i < total_regs; i++)
+ sim_regno[i] = -1;
+
+ /* General-purpose registers. */
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
+
+ /* Floating-point registers. */
+ if (tdep->ppc_fp0_regnum >= 0)
+ for (i = 0; i < ppc_num_fprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_fp0_regnum + i,
+ sim_ppc_f0_regnum + i);
+ if (tdep->ppc_fpscr_regnum >= 0)
+ set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
+
+ set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
+ set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
+ set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
+
+ /* Segment registers. */
+ if (tdep->ppc_sr0_regnum >= 0)
+ for (i = 0; i < ppc_num_srs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_sr0_regnum + i,
+ sim_ppc_sr0_regnum + i);
+
+ /* Altivec registers. */
+ if (tdep->ppc_vr0_regnum >= 0)
+ {
+ for (i = 0; i < ppc_num_vrs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_vr0_regnum + i,
+ sim_ppc_vr0_regnum + i);
+
+ /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
+ we can treat this more like the other cases. */
+ set_sim_regno (sim_regno,
+ tdep->ppc_vr0_regnum + ppc_num_vrs,
+ sim_ppc_vscr_regnum);
+ }
+ /* vsave is a special-purpose register, so the code below handles it. */
+
+ /* SPE APU (E500) registers. */
+ if (tdep->ppc_ev0_regnum >= 0)
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_ev0_regnum + i,
+ sim_ppc_ev0_regnum + i);
+ if (tdep->ppc_ev0_upper_regnum >= 0)
+ for (i = 0; i < ppc_num_gprs; i++)
+ set_sim_regno (sim_regno,
+ tdep->ppc_ev0_upper_regnum + i,
+ sim_ppc_rh0_regnum + i);
+ if (tdep->ppc_acc_regnum >= 0)
+ set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
+ /* spefscr is a special-purpose register, so the code below handles it. */
+
+ /* Now handle all special-purpose registers. Verify that they
+ haven't mistakenly been assigned numbers by any of the above
+ code). */
+ for (i = 0; i < total_regs; i++)
+ if (regs[i].spr_num >= 0)
+ set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
+
+ /* Drop the initialized array into place. */
+ tdep->sim_regno = sim_regno;
+}
+
+
+/* Given a GDB register number REG, return the corresponding SIM
+ register number. */
+static int
+rs6000_register_sim_regno (int reg)
+{
+ struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
+ int sim_regno;
+
+ gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
+ sim_regno = tdep->sim_regno[reg];
+
+ if (sim_regno >= 0)
+ return sim_regno;
+ else
+ return LEGACY_SIM_REGNO_IGNORE;
+}
+
+\f
+
+/* Register set support functions. */
+
+static void
+ppc_supply_reg (struct regcache *regcache, int regnum,
+ const gdb_byte *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_supply (regcache, regnum, regs + offset);
+}
+
+static void
+ppc_collect_reg (const struct regcache *regcache, int regnum,
+ gdb_byte *regs, size_t offset)
+{
+ if (regnum != -1 && offset != -1)
+ regcache_raw_collect (regcache, regnum, regs + offset);
+}
+
+/* Supply register REGNUM in the general-purpose register set REGSET
+ from the buffer specified by GREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
+ i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
+}
+
+/* Supply register REGNUM in the floating-point register set REGSET
+ from the buffer specified by FPREGS and LEN to register cache
+ REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
+
+void
+ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
+ int regnum, const void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i < tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 8)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_supply_reg (regcache, i, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+
+/* Collect register REGNUM in the general-purpose register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ GREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_gregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *gregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ offset = offsets->r0_offset;
+ for (i = tdep->ppc_gp0_regnum;
+ i < tdep->ppc_gp0_regnum + ppc_num_gprs;
+ i++, offset += 4)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, i, gregs, offset);
+ }
+
+ if (regnum == -1 || regnum == PC_REGNUM)
+ ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
+ gregs, offsets->ps_offset);
+ if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
+ gregs, offsets->cr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
+ gregs, offsets->lr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
+ gregs, offsets->ctr_offset);
+ if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
+ gregs, offsets->xer_offset);
+ if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
+ gregs, offsets->mq_offset);
+}
+
+/* Collect register REGNUM in the floating-point register set
+ REGSET. from register cache REGCACHE into the buffer specified by
+ FPREGS and LEN. If REGNUM is -1, do this for all registers in
+ REGSET. */
+
+void
+ppc_collect_fpregset (const struct regset *regset,
+ const struct regcache *regcache,
+ int regnum, void *fpregs, size_t len)
+{
+ struct gdbarch *gdbarch = get_regcache_arch (regcache);
+ struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+ const struct ppc_reg_offsets *offsets = regset->descr;
+ size_t offset;
+ int i;
+
+ gdb_assert (ppc_floating_point_unit_p (gdbarch));
+
+ offset = offsets->f0_offset;
+ for (i = tdep->ppc_fp0_regnum;
+ i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
+ i++, offset += 8)
+ {
+ if (regnum == -1 || regnum == i)
+ ppc_collect_reg (regcache, i, fpregs, offset);
+ }
+
+ if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
+ ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
+ fpregs, offsets->fpscr_offset);
+}
+\f
+