* Cleanup lowboot code for MPC5200

[people/ms/u-boot.git] / CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index c30172b65e98b9108a35335f102af599712f2a9a..4745c8f511e37a1997aed6e9b01ad8faa3150b04 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,57 @@
 Changes since U-Boot 1.0.0:
 ======================================================================
 
+* Minor code cleanup (coding style)
+
+* Patch by Reinhard Meyer, 30 Dec 2003:
+  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
+  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
+  - turned debug print of PHY registers into a function (called in two places)
+  - added support for EMK MPC5200 based modules
+
+* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+
+* Add support for TQM866M modules
+
+* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+
+* Fix a few compiler warnings
+
+* Patch by Reinhard Meyer, 28 Dec 2003:
+  Add initial support for TOP5200 board
+
+* Make CPU clock on ICA-IP board controllable by a "cpuclk"
+  environment variable which can set to "100", "133", or "150". The
+  CPU clock will be configured accordingly upon next reboot. Other
+  values are ignored. In case of an invalid or undefined "cpuclk"
+  value, the compile-time default CPU clock speed will be used.
+
+* Enable Quad-UART on BMS2003 board (initialize the PCMCIA memory
+  window that is used to access the UART registers by the Linux driver)
+
+* Patch by Reinhard Meyer, 20 Dec 2003:
+  Fix clock calculation for the MPC5200 for higher clock frequencies
+  (above 2**32 / 10 = 429.5 MHz).
+
+* Fix CONFIG_PLL_PCI_TO_MEM_MULTIPLIER divider error in SP8240 configuration
+
+* Fix IceCube CLKIN configuration (it's 33.000000MHz)
+
+* Add new configuration for IceCube board with DDR memory
+
+* Update TRAB memory configurations
+
+* Add JFFS2 support for INCA-IP board
+
+* Patch by Bill Hargen, 09 Dec 2003:
+  - BUBINGA405EP: changed flash driver to protect top sector containing
+    first instruction.
+  - BUBINGA405EP: configured "eeprom" command to access boot config EEPROM.
+  - BUBINGA405EP: fixed PLL init (init chip selects before FPGA/NVRAM access).
+  - 405EP: fixed SPD-based SDRAM init (only use banks 0 and 1).
+  - 405EP: added/fixed support for "reginfo" command.
+  - 4xx: removed spurious MII error messages on "mii info" command.
+
 * Patch by Bernhard Kuhn, 28 Nov 2003:
   add support for Coldfire CPU
   add support for Motorola M5272C3 and M5282EVB boards