powerpc/mpc85xx: Avoid hardcoding in SPL linker script

[people/ms/u-boot.git] / README

diff --git a/README b/README
index cb96322fb71d0e4301182759fa53c4afdc6b3167..017a13df4da702175a87ca5be8791691df017d37 100644 (file)
--- a/README
+++ b/README
@@ -431,6 +431,10 @@ The following options need to be configured:
                This CONFIG is defined when the CPC is configured as SRAM at the
                time of U-boot entry and is required to be re-initialized.
 
+               CONFIG_DEEP_SLEEP
+               Inidcates this SoC supports deep sleep feature. If deep sleep is
+               supported, core will start to execute uboot when wakes up.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -458,6 +462,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
@@ -473,7 +480,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian