Makefile: Add support of CONFIG_SPL_FSL_PBL

[people/ms/u-boot.git] / README

diff --git a/README b/README
index 216f0c70aa9403534127dcd256627fa55e12f08e..49dcd37a3c859484247e764b3a8551b9f6bfc787 100644 (file)
--- a/README
+++ b/README
@@ -427,6 +427,14 @@ The following options need to be configured:
                In this mode, a single differential clock is used to supply
                clocks to the sysclock, ddrclock and usbclock.
 
+               CONFIG_SYS_CPC_REINIT_F
+               This CONFIG is defined when the CPC is configured as SRAM at the
+               time of U-boot entry and is required to be re-initialized.
+
+               CONFIG_DEEP_SLEEP
+               Inidcates this SoC supports deep sleep feature. If deep sleep is
+               supported, core will start to execute uboot when wakes up.
+
 - Generic CPU options:
                CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
@@ -454,6 +462,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_DDRC_GEN3
                Freescale DDR3 controller.
 
+               CONFIG_SYS_FSL_DDRC_GEN4
+               Freescale DDR4 controller.
+
                CONFIG_SYS_FSL_DDRC_ARM_GEN3
                Freescale DDR3 controller for ARM-based SoCs.
 
@@ -469,7 +480,15 @@ The following options need to be configured:
 
                CONFIG_SYS_FSL_DDR3
                Board config to use DDR3. It can be enabled for SoCs with
-               Freescale DDR3 controllers.
+               Freescale DDR3 or DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR3L
+               Board config to use DDR3L. It can be enabled for SoCs with
+               DDR3L controllers.
+
+               CONFIG_SYS_FSL_DDR4
+               Board config to use DDR4. It can be enabled for SoCs with
+               DDR4 controllers.
 
                CONFIG_SYS_FSL_IFC_BE
                Defines the IFC controller register space as Big Endian
@@ -486,6 +505,10 @@ The following options need to be configured:
                PBI commands can be used to configure SoC before it starts the execution.
                Please refer doc/README.pblimage for more details
 
+               CONFIG_SPL_FSL_PBL
+               It adds a target to create boot binary having SPL binary in PBI format
+               concatenated with u-boot binary.
+
                CONFIG_SYS_FSL_DDR_BE
                Defines the DDR controller register space as Big Endian
 
@@ -566,6 +589,8 @@ The following options need to be configured:
                CONFIG_ARM_ERRATA_742230
                CONFIG_ARM_ERRATA_743622
                CONFIG_ARM_ERRATA_751472
+               CONFIG_ARM_ERRATA_794072
+               CONFIG_ARM_ERRATA_761320
 
                If set, the workarounds for these ARM errata are applied early
                during U-Boot startup. Note that these options force the
@@ -910,6 +935,7 @@ The following options need to be configured:
                The default command configuration includes all commands
                except those marked below with a "*".
 
+               CONFIG_CMD_AES            AES 128 CBC encrypt/decrypt
                CONFIG_CMD_ASKENV       * ask for env variable
                CONFIG_CMD_BDI            bdinfo
                CONFIG_CMD_BEDBUG       * Include BedBug Debugger
@@ -1012,7 +1038,7 @@ The following options need to be configured:
                CONFIG_CMD_CDP          * Cisco Discover Protocol support
                CONFIG_CMD_MFSL         * Microblaze FSL support
                CONFIG_CMD_XIMG           Load part of Multi Image
-
+               CONFIG_CMD_UUID         * Generate random UUID or GUID string
 
                EXAMPLE: If you want all functions except of network
                support you can write:
@@ -1525,6 +1551,16 @@ The following options need to be configured:
                this to the maximum filesize (in bytes) for the buffer.
                Default is 4 MiB if undefined.
 
+               DFU_DEFAULT_POLL_TIMEOUT
+               Poll timeout [ms], is the timeout a device can send to the
+               host. The host must wait for this timeout before sending
+               a subsequent DFU_GET_STATUS request to the device.
+
+               DFU_MANIFEST_POLL_TIMEOUT
+               Poll timeout [ms], which the device sends to the host when
+               entering dfuMANIFEST state. Host waits this timeout, before
+               sending again an USB request to the device.
+
 - Journaling Flash filesystem support:
                CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
                CONFIG_JFFS2_NAND_DEV
@@ -3300,6 +3336,9 @@ FIT uImage format:
                continuing (the hardware starts execution after just
                loading the first page rather than the full 4K).
 
+               CONFIG_SPL_SKIP_RELOCATE
+               Avoid SPL relocation
+
                CONFIG_SPL_NAND_BASE
                Include nand_base.c in the SPL.  Requires
                CONFIG_SPL_NAND_DRIVERS.
@@ -4485,8 +4524,13 @@ This firmware often needs to be loaded during U-Boot booting, so macros
 are used to identify the storage device (NOR flash, SPI, etc) and the address
 within that device.
 
-- CONFIG_SYS_QE_FMAN_FW_ADDR
-       The address in the storage device where the firmware is located.  The
+- CONFIG_SYS_FMAN_FW_ADDR
+       The address in the storage device where the FMAN microcode is located.  The
+       meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
+       is also specified.
+
+- CONFIG_SYS_QE_FW_ADDR
+       The address in the storage device where the QE microcode is located.  The
        meaning of this address depends on which CONFIG_SYS_QE_FW_IN_xxx macro
        is also specified.