arc: add support for SLC (System Level Cache, AKA L2-cache)

[people/ms/u-boot.git] / arch / arc / include / asm / arcregs.h

diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 5d48d11bab6b76e2878b69e2ecb7742dd90beca2..0e11dcced5c87db6e8b8d6c06ac21ed8c0ff9e1f 100644 (file)
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -7,6 +7,8 @@
 #ifndef _ASM_ARC_ARCREGS_H
 #define _ASM_ARC_ARCREGS_H
 
+#include <asm/cache.h>
+
 /*
  * ARC architecture has additional address space - auxiliary registers.
  * These registers are mostly used for configuration purposes.
@@ -21,9 +23,10 @@
 #define ARC_AUX_IC_IVIC                0x10
 #define ARC_AUX_IC_CTRL                0x11
 #define ARC_AUX_IC_IVIL                0x19
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
 #define ARC_AUX_IC_PTAG                0x1E
 #endif
+#define ARC_BCR_IC_BUILD       0x77
 
 /* Timer related auxiliary registers */
 #define ARC_AUX_TIMER0_CNT     0x21    /* Timer 0 count */
@@ -39,9 +42,14 @@
 #define ARC_AUX_DC_IVDL                0x4A
 #define ARC_AUX_DC_FLSH                0x4B
 #define ARC_AUX_DC_FLDL                0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
+#if (CONFIG_ARC_MMU_VER == 3)
 #define ARC_AUX_DC_PTAG                0x5C
 #endif
+#define ARC_BCR_DC_BUILD       0x72
+#define ARC_BCR_SLC            0xce
+#define ARC_AUX_SLC_CONTROL    0x903
+#define ARC_AUX_SLC_FLUSH      0x904
+#define ARC_AUX_SLC_INVALIDATE 0x905
 
 #ifndef __ASSEMBLY__
 /* Accessors for auxiliary registers */