ARM: Introduce erratum workaround for 454179

[people/ms/u-boot.git] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index fdc05b942f15bb80415c295faba6832e689d8b01..8483687879ed70054deb33cc4f56e22780ac1544 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -31,9 +31,12 @@
  *************************************************************************/
 
        .globl  reset
+       .globl  save_boot_params_ret
 
 reset:
-       bl      save_boot_params
+       /* Allow the board to save important registers */
+       b       save_boot_params
+save_boot_params_ret:
        /*
         * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
         * except if in HYP mode already
@@ -52,10 +55,10 @@ reset:
  * Continue to use ROM code vector only in OMAP4 spl)
  */
 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
-       /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
-       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
+       /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
+       mrc     p15, 0, r0, c1, c0, 0   @ Read CP15 SCTLR Register
        bic     r0, #CR_V               @ V = 0
-       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
+       mcr     p15, 0, r0, c1, c0, 0   @ Write CP15 SCTLR Register
 
        /* Set vector address in CP15 VBAR register */
        ldr     r0, =_start
@@ -96,7 +99,7 @@ ENDPROC(c_runtime_cpu_setup)
  *
  *************************************************************************/
 ENTRY(save_boot_params)
-       bx      lr                      @ back to my caller
+       b       save_boot_params_ret            @ back to my caller
 ENDPROC(save_boot_params)
        .weak   save_boot_params
 
@@ -163,7 +166,43 @@ ENTRY(cpu_init_cp15)
        mcr     p15, 0, r0, c15, c0, 1  @ write diagnostic register
 #endif
 
-       mov     pc, lr                  @ back to my caller
+       mov     r5, lr                  @ Store my Caller
+       mrc     p15, 0, r1, c0, c0, 0   @ r1 has Read Main ID Register (MIDR)
+       mov     r3, r1, lsr #20         @ get variant field
+       and     r3, r3, #0xf            @ r3 has CPU variant
+       and     r4, r1, #0xf            @ r4 has CPU revision
+       mov     r2, r3, lsl #4          @ shift variant field for combined value
+       orr     r2, r4, r2              @ r2 has combined CPU variant + revision
+
+#ifdef CONFIG_ARM_ERRATA_798870
+       cmp     r2, #0x30               @ Applies to lower than R3p0
+       bge     skip_errata_798870      @ skip if not affected rev
+       cmp     r2, #0x20               @ Applies to including and above R2p0
+       blt     skip_errata_798870      @ skip if not affected rev
+
+       mrc     p15, 1, r0, c15, c0, 0  @ read l2 aux ctrl reg
+       orr     r0, r0, #1 << 7         @ Enable hazard-detect timeout
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_l2aux_ctrl
+       isb                             @ Recommended ISB after l2actlr update
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+skip_errata_798870:
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_454179
+       cmp     r2, #0x21               @ Only on < r2p1
+       bge     skip_errata_454179
+
+       mrc     p15, 0, r0, c1, c0, 1   @ Read ACR
+       orr     r0, r0, #(0x3 << 6)     @ Set DBSM(BIT7) and IBE(BIT6) bits
+       push    {r1-r5}                 @ Save the cpu info registers
+       bl      v7_arch_cp15_set_acr
+       pop     {r1-r5}                 @ Restore the cpu info - fall through
+
+skip_errata_454179:
+#endif
+
+       mov     pc, r5                  @ back to my caller
 ENDPROC(cpu_init_cp15)
 
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT