dts: meson: Switch GXL, GXM & AXG to using upstream DT

[thirdparty/u-boot.git] / arch / arm / dts / meson-gxm.dtsi

diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi
index b6f89f108e2829ec94e734eff0f130c74f2d2d68..411cc312fc62bdf929b6992f2c3687c7dffda397 100644 (file)
--- a/arch/arm/dts/meson-gxm.dtsi
+++ b/arch/arm/dts/meson-gxm.dtsi
@@ -42,11 +42,28 @@
                        };
                };
 
+               cpu0: cpu@0 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu1: cpu@1 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu2: cpu@2 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu3: cpu@3 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
                cpu4: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -57,6 +74,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -67,6 +85,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -77,11 +96,41 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
                };
        };
+
+       gpu_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-125000000 {
+                       opp-hz = /bits/ 64 <125000000>;
+                       opp-microvolt = <950000>;
+               };
+               opp-250000000 {
+                       opp-hz = /bits/ 64 <250000000>;
+                       opp-microvolt = <950000>;
+               };
+               opp-285714285 {
+                       opp-hz = /bits/ 64 <285714285>;
+                       opp-microvolt = <950000>;
+               };
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       opp-microvolt = <950000>;
+               };
+               opp-500000000 {
+                       opp-hz = /bits/ 64 <500000000>;
+                       opp-microvolt = <950000>;
+               };
+               opp-666666666 {
+                       opp-hz = /bits/ 64 <666666666>;
+                       opp-microvolt = <950000>;
+               };
+       };
 };
 
 &apb {
@@ -106,21 +155,7 @@
                interrupt-names = "job", "mmu", "gpu";
                clocks = <&clkc CLKID_MALI>;
                resets = <&reset RESET_MALI_CAPB3>, <&reset RESET_MALI>;
-
-               /*
-                * Mali clocking is provided by two identical clock paths
-                * MALI_0 and MALI_1 muxed to a single clock by a glitch
-                * free mux to safely change frequency while running.
-                */
-               assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
-                                 <&clkc CLKID_MALI_0>,
-                                 <&clkc CLKID_MALI>; /* Glitch free mux */
-               assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
-                                        <0>, /* Do Nothing */
-                                        <&clkc CLKID_MALI_0>;
-               assigned-clock-rates = <0>, /* Do Nothing */
-                                      <666666666>,
-                                      <0>; /* Do Nothing */
+               operating-points-v2 = <&gpu_opp_table>;
        };
 };
 
@@ -169,8 +204,11 @@
        compatible = "amlogic,meson-gxm-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 };
 
-&dwc3 {
-       phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
+&usb {
+       compatible = "amlogic,meson-gxm-usb-ctrl";
+
+       phy-names = "usb2-phy0", "usb2-phy1", "usb2-phy2";
+       phys = <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
 };
 
 &vdec {