dts: meson: Switch GXL, GXM & AXG to using upstream DT

[thirdparty/u-boot.git] / arch / arm / dts / meson-gxm.dtsi

diff --git a/arch/arm/dts/meson-gxm.dtsi b/arch/arm/dts/meson-gxm.dtsi
index fe4145112295cb720377264fe1bb836da08e034c..411cc312fc62bdf929b6992f2c3687c7dffda397 100644 (file)
--- a/arch/arm/dts/meson-gxm.dtsi
+++ b/arch/arm/dts/meson-gxm.dtsi
@@ -42,11 +42,28 @@
                        };
                };
 
+               cpu0: cpu@0 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu1: cpu@1 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu2: cpu@2 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
+               cpu3: cpu@3 {
+                       capacity-dmips-mhz = <1024>;
+               };
+
                cpu4: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -57,6 +74,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -67,6 +85,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;
@@ -77,6 +96,7 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 1>;
                        #cooling-cells = <2>;