#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
+ operating-points-v2 = <&cpu_opp_table>;
reg = <0x0>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ };
+
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000000>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <600>;
+ min-residency-us = <10000>;
+ };
+ };
+ };
+
+ cpu_opp_table: cpu_opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp00 {
+ opp-hz = /bits/ 64 <1199999988>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <599999994>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <399999996>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <299999997>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <500000>;
};
};
};
pd_dp: pd-dp {
- /* fixme: what to attach to */
#power-domain-cells = <0x0>;
pd-id = <0x29>;
};
firmware {
compatible = "xlnx,zynqmp-pm";
method = "smc";
+ interrupt-parent = <&gic>;
+ interrupts = <0 35 4>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
- interrupts = <1 13 0xf01>,
- <1 14 0xf01>,
- <1 11 0xf01>,
- <1 10 0xf01>;
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
};
edac {
compatible = "arm,cortex-a53-edac";
};
- pcap {
+ fpga_full: fpga-full {
+ compatible = "fpga-region";
+ fpga-mgr = <&pcap>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc_revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
+
+ pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "arm,mali-400", "arm,mali-utgard";
- reg = <0x0 0xfd4b0000 0x0 0x30000>;
+ reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
+ clock-names = "gpu", "gpu_pp0", "gpu_pp1";
power-domains = <&pd_gpu>;
};
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
+ gpio-controller;
power-domains = <&pd_gpio>;
};
i2c0: i2c@ff020000 {
- compatible = "cdns,i2c-r1p10";
+ compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
};
i2c1: i2c@ff030000 {
- compatible = "cdns,i2c-r1p10";
+ compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
+ bus-range = <0x00 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
+ calibration = <0x8000>;
};
serdes: zynqmp_phy@fd400000 {
<0x0 0xfd1a0000 0x0 0x1000>,
<0x0 0xff5e0000 0x0 0x1000>;
reg-names = "serdes", "siou", "fpd", "lpd";
- xlnx,tx_termination_fix;
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
lane0: lane0 {
#phy-cells = <4>;
};
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&pd_sata>;
+ #stream-id-cells = <4>;
+ iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
+ <&smmu 0x4c2>, <&smmu 0x4c3>;
+ /* dma-coherent; */
};
sdhci0: sdhci@ff160000 {
power-domains = <&pd_sd1>;
};
+ pinctrl0: pinctrl@ff180000 {
+ compatible = "xlnx,pinctrl-zynqmp";
+ status = "disabled";
+ reg = <0x0 0xff180000 0x0 0x1000>;
+ };
+
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x0 0x20000>;
#iommu-cells = <1>;
+ status = "disabled";
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
- mmu-masters = < &gem0 0x874
- &gem1 0x875
- &gem2 0x876
- &gem3 0x877
- &usb0 0x860
- &usb1 0x861
- &qspi 0x873
- &lpd_dma_chan1 0x868
- &lpd_dma_chan2 0x869
- &lpd_dma_chan3 0x86a
- &lpd_dma_chan4 0x86b
- &lpd_dma_chan5 0x86c
- &lpd_dma_chan6 0x86d
- &lpd_dma_chan7 0x86e
- &lpd_dma_chan8 0x86f
- &fpd_dma_chan1 0x14e8
- &fpd_dma_chan2 0x14e9
- &fpd_dma_chan3 0x14ea
- &fpd_dma_chan4 0x14eb
- &fpd_dma_chan5 0x14ec
- &fpd_dma_chan6 0x14ed
- &fpd_dma_chan7 0x14ee
- &fpd_dma_chan8 0x14ef
- &sdhci0 0x870
- &sdhci1 0x871
- &nand0 0x872>;
};
spi0: spi@ff040000 {
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "aclk", "aud_clk";
+ power-domains = <&pd_dp>;
xlnx,dp-version = "v1.2";
xlnx,max-lanes = <2>;
xlnx,max-link-rate = <540000>;
xlnx,output-fmt = "rgb";
xlnx,vid-fmt = "yuyv";
xlnx,gfx-fmt = "rgb565";
+ power-domains = <&pd_dp>;
};
xlnx_dpdma: dma@fd4c0000 {
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
+ power-domains = <&pd_dp>;
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel {
projects / people / ms / u-boot.git / blobdiff