#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
#include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT 6
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#endif
+
#define CONFIG_MP
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
/* Link Definitions */
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
0x18A0)
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-
/* IFC */
#define CONFIG_SYS_FSL_IFC_LE
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+
#ifdef CONFIG_LS2085A
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#ifdef CONFIG_LS2085A
#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
#endif
#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */