ROCKCHIP_SYSCON_GRF,
ROCKCHIP_SYSCON_SGRF,
ROCKCHIP_SYSCON_PMU,
+ ROCKCHIP_SYSCON_PMUGRF,
+ ROCKCHIP_SYSCON_PMUSGRF,
+ ROCKCHIP_SYSCON_CIC,
+ ROCKCHIP_SYSCON_MSCH,
};
/* Standard Rockchip clock numbers */
return clk_id - 1;
}
+struct sysreset_reg {
+ unsigned int glb_srst_fst_value;
+ unsigned int glb_srst_snd_value;
+};
+
/**
* clk_get_divisor() - Calculate the required clock divisior
*
*/
void *rockchip_get_cru(void);
+/**
+ * rockchip_get_pmucru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_pmucru(void);
+
struct rk3288_cru;
struct rk3288_grf;
-void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf);
+
+int rockchip_get_clk(struct udevice **devp);
#endif