ARM: tegra: add peripheral clock init table

[people/ms/u-boot.git] / arch / arm / include / asm / arch-tegra / clock.h

diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index 04011ae25585aff7f13e2b763b943a11571aeafc..e0737f574addb3dd04f5cdaf0e8be1b415fa4641 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -16,6 +16,8 @@ enum clock_osc_freq {
        CLOCK_OSC_FREQ_19_2,
        CLOCK_OSC_FREQ_12_0,
        CLOCK_OSC_FREQ_26_0,
+       CLOCK_OSC_FREQ_38_4,
+       CLOCK_OSC_FREQ_48_0,
 
        CLOCK_OSC_FREQ_COUNT,
 };
@@ -42,6 +44,9 @@ enum {
 /* return the current oscillator clock frequency */
 enum clock_osc_freq clock_get_osc_freq(void);
 
+/* return the clk_m frequency */
+unsigned int clk_m_get_rate(unsigned int parent_rate);
+
 /**
  * Start PLL using the provided configuration parameters.
  *
@@ -319,7 +324,7 @@ enum periph_id clk_id_to_periph_id(int clk_id);
  * @param p post divider(DIVP)
  * @param cpcon base PLL charge pump(CPCON)
  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
- *              be overriden), 1 if PLL is already correct
+ *              be overridden), 1 if PLL is already correct
  */
 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
 
@@ -336,4 +341,39 @@ void arch_timer_init(void);
 
 void tegra30_set_up_pllp(void);
 
+/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
+#define CLOCK_ID_PLL_COUNT     (CLOCK_ID_COUNT - 3)
+
+struct clk_pll_info {
+       u32     m_shift:5;      /* DIVM_SHIFT */
+       u32     n_shift:5;      /* DIVN_SHIFT */
+       u32     p_shift:5;      /* DIVP_SHIFT */
+       u32     kcp_shift:5;    /* KCP/cpcon SHIFT */
+       u32     kvco_shift:5;   /* KVCO/lfcon SHIFT */
+       u32     lock_ena:6;     /* LOCK_ENABLE/EN_LOCKDET shift */
+       u32     rsvd:1;
+       u32     m_mask:10;      /* DIVM_MASK */
+       u32     n_mask:12;      /* DIVN_MASK */
+       u32     p_mask:10;      /* DIVP_MASK or VCO_MASK */
+       u32     kcp_mask:10;    /* KCP/CPCON MASK */
+       u32     kvco_mask:10;   /* KVCO/LFCON MASK */
+       u32     lock_det:6;     /* LOCK_DETECT/LOCKED shift */
+       u32     rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
+struct periph_clk_init {
+       enum periph_id periph_id;
+       enum clock_id parent_clock_id;
+};
+extern struct periph_clk_init periph_clk_init_table[];
+
+/**
+ * Enable output clock for external peripherals
+ *
+ * @param clk_id       Clock ID to output (1, 2 or 3)
+ * @return 0 if OK. -ve on error
+ */
+int clock_external_output(int clk_id);
+
 #endif  /* _TEGRA_CLOCK_H_ */