arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL

[people/ms/u-boot.git] / arch / arm / mach-mvebu / cpu.c

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index 38e15aa7b67b07a9b6e97e9b20deffa88a557c7c..895ad929b10721e4f1d28c0402efd71fc97ade42 100644 (file)
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -18,14 +18,6 @@
 #define DDR_SIZE_CS_OFF(n)     (0x0004 + ((n) << 3))
 
 static struct mbus_win windows[] = {
-       /* PCIE MEM address space */
-       { MBUS_PCI_MEM_BASE, MBUS_PCI_MEM_SIZE,
-         CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
-
-       /* PCIE IO address space */
-       { MBUS_PCI_IO_BASE, MBUS_PCI_IO_SIZE,
-         CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
-
        /* SPI */
        { MBUS_SPI_BASE, MBUS_SPI_SIZE,
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
@@ -35,6 +27,14 @@ static struct mbus_win windows[] = {
          CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
+void lowlevel_init(void)
+{
+       /*
+        * Dummy implementation, we only need LOWLEVEL_INIT
+        * on Armada to configure CP15 in start.S / cpu_init_cp15()
+        */
+}
+
 void reset_cpu(unsigned long ignored)
 {
        struct mvebu_system_registers *reg =
@@ -179,35 +179,82 @@ static void set_cbar(u32 addr)
        asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
 }
 
+#define MV_USB_PHY_BASE                        (MVEBU_AXP_USB_BASE + 0x800)
+#define MV_USB_PHY_PLL_REG(reg)                (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
+#define MV_USB_X3_BASE(addr)           (MVEBU_AXP_USB_BASE | BIT(11) | \
+                                        (((addr) & 0xF) << 6))
+#define MV_USB_X3_PHY_CHANNEL(dev, reg)        (MV_USB_X3_BASE((dev) + 1) |    \
+                                        (((reg) & 0xF) << 2))
 
-int arch_cpu_init(void)
+static void setup_usb_phys(void)
 {
-#ifndef CONFIG_SPL_BUILD
-       if (mvebu_soc_family() == MVEBU_SOC_A38X) {
-               struct pl310_regs *const pl310 =
-                       (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+       int dev;
 
-               /*
-                * Only with disabled MMU its possible to switch the base
-                * register address on Armada 38x. Without this the SDRAM
-                * located at >= 0x4000.0000 is also not accessible, as its
-                * still locked to cache.
-                *
-                * So to fully release / unlock this area from cache, we need
-                * to first flush all caches, then disable the MMU and
-                * disable the L2 cache.
-                */
-               icache_disable();
-               dcache_disable();
-               mmu_disable();
-               clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+       /*
+        * USB PLL init
+        */
+
+       /* Setup PLL frequency */
+       /* USB REF frequency = 25 MHz */
+       clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
+
+       /* Power up PLL and PHY channel */
+       clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
+
+       /* Assert VCOCAL_START */
+       clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
+
+       mdelay(1);
+
+       /*
+        * USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
+        */
+
+       for (dev = 0; dev < 3; dev++) {
+               clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
+
+               /* Assert REG_RCAL_START in channel REG 1 */
+               clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
+               udelay(40);
+               clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
        }
+}
+
+int arch_cpu_init(void)
+{
+#if !defined(CONFIG_SPL_BUILD)
+       struct pl310_regs *const pl310 =
+               (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
+       /*
+        * Only with disabled MMU its possible to switch the base
+        * register address on Armada 38x. Without this the SDRAM
+        * located at >= 0x4000.0000 is also not accessible, as its
+        * still locked to cache.
+        */
+       mmu_disable();
 #endif
 
        /* Linux expects the internal registers to be at 0xf1000000 */
        writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
        set_cbar(SOC_REGS_PHY_BASE + 0xC000);
 
+#if !defined(CONFIG_SPL_BUILD)
+       /*
+        * From this stage on, the SoC detection is working. As we have
+        * configured the internal register base to the value used
+        * in the macros / defines in the U-Boot header (soc.h).
+        */
+
+       /*
+        * To fully release / unlock this area from cache, we need
+        * to flush all caches and disable the L2 cache.
+        */
+       icache_disable();
+       dcache_disable();
+       clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+#endif
+
        /*
         * We need to call mvebu_mbus_probe() before calling
         * update_sdram_window_sizes() as it disables all previously
@@ -246,6 +293,9 @@ int arch_cpu_init(void)
                clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
                                GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
                                NAND_PUP_EN | SPI_PUP_EN);
+
+               /* Configure USB PLL and PHYs on AXP */
+               setup_usb_phys();
        }
 
        /* Enable NAND and NAND arbiter */