]> git.ipfire.org Git - people/ms/u-boot.git/blobdiff - arch/arm/mach-socfpga/Kconfig
arm: socfpga: Enable build for Arria 10
[people/ms/u-boot.git] / arch / arm / mach-socfpga / Kconfig
index 18bb6dce3c86c18d6dfcb68c70968b13f184bb09..2563e7926d1d80a2fc4770e7cf10f2aa60c978db 100644 (file)
@@ -37,17 +37,25 @@ config TARGET_SOCFPGA_ARRIA5
        bool
        select TARGET_SOCFPGA_GEN5
 
+config TARGET_SOCFPGA_ARRIA10
+       bool
+
 config TARGET_SOCFPGA_CYCLONE5
        bool
        select TARGET_SOCFPGA_GEN5
 
 config TARGET_SOCFPGA_GEN5
        bool
+       select ALTERA_SDRAM
 
 choice
        prompt "Altera SOCFPGA board select"
        optional
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+       bool "Altera SOCFPGA SoCDK (Arria 10)"
+       select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_ARRIA5_SOCDK
        bool "Altera SOCFPGA SoCDK (Arria V)"
        select TARGET_SOCFPGA_ARRIA5
@@ -81,6 +89,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
        bool "Terasic DE0-Nano-Atlas (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+       bool "Terasic DE10-Nano (Cyclone V)"
+       select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
        bool "Terasic DE1-SoC (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -93,9 +105,11 @@ endchoice
 
 config SYS_BOARD
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "is1" if TARGET_SOCFPGA_IS1
        default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -105,12 +119,14 @@ config SYS_BOARD
 
 config SYS_VENDOR
        default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
        default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
 
 config SYS_SOC
@@ -118,9 +134,11 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+       default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
        default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+       default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
        default "socfpga_is1" if TARGET_SOCFPGA_IS1
        default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT