/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2012-2015 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/sizes.h>
#include <asm/system.h>
-#include "ssc-regs.h"
-
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0
-#ifdef CONFIG_DEBUG_LL
- bl debug_ll_init
-#endif
-
- bl setup_init_ram @ RAM area for stack and page talbe
+ bl setup_init_ram @ RAM area for stack and page table
/*
* Now we are using the page table embedded in the Boot ROM.
- * It is not handy since it is not a straight mapped table for sLD3.
- * Also, the access to the external bus is prohibited. What we need
- * to do next is to create a page table and switch over to it.
+ * What we need to do next is to create a page table and switch
+ * over to it.
*/
bl create_page_table
bl __v7_flush_dcache_all
bl enable_mmu
+#ifdef CONFIG_DEBUG_LL
+ bl debug_ll_init
+#endif
+
mov lr, r8 @ restore link
mov pc, lr @ back to my caller
ENDPROC(lowlevel_init)
*/
#define BOOT_RAM_SIZE (SZ_32K)
#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
-#define BOOT_WAY_BITS (0x00000100) /* way 8 */
+#define BOOT_RAM_WAYS (0x00000100) @ way 8
+
+#define SSCO_BASE 0x506c0000
+#define SSCOPE 0x244
+#define SSCOQM 0x248
+#define SSCOQAD 0x24c
+#define SSCOQSZ 0x250
+#define SSCOQWN 0x258
+#define SSCOPPQSEF 0x25c
+#define SSCOLPQS 0x260
ENTRY(setup_init_ram)
- /*
- * Touch to zero for the boot way
- */
-0:
- /*
- * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
- */
- ldr r0, = 0x00408006 @ touch to zero with address range
- ldr r1, = SSCOQM
- str r0, [r1]
+ ldr r1, = SSCO_BASE
+ mrc p15, 0, r0, c2, c0, 0 @ TTBR0
+ ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
+ bfc r0, #0, #20
+ cmp r0, #0x50000000 @ is sLD3 page table?
+ biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
+
+ /* Touch to zero for the boot way */
+0: ldr r0, = 0x00408006 @ touch to zero with address range
+ str r0, [r1, #SSCOQM]
ldr r0, = BOOT_RAM_BASE
- ldr r1, = SSCOQAD
- str r0, [r1]
+ str r0, [r1, #SSCOQAD]
ldr r0, = BOOT_RAM_SIZE
- ldr r1, = SSCOQSZ
- str r0, [r1]
- ldr r0, = BOOT_WAY_BITS
- ldr r1, = SSCOQWN
- str r0, [r1]
- ldr r1, = SSCOPPQSEF
- ldr r0, [r1]
+ str r0, [r1, #SSCOQSZ]
+ ldr r0, = BOOT_RAM_WAYS
+ str r0, [r1, #SSCOQWN]
+ ldr r0, [r1, #SSCOPPQSEF]
cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurs
- ldr r1, = SSCOLPQS
-1:
- ldr r0, [r1]
+1: ldr r0, [r1, #SSCOLPQS]
cmp r0, #0x4
bne 1b @ wait until the operation is completed
- str r0, [r1] @ clear the complete notification flag
+ str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
mov pc, lr
ENDPROC(setup_init_ram)