ARM: uniphier: adjust ifdefs for new UniPhier DWC3 CONFIG

[people/ms/u-boot.git] / arch / arm / mach-uniphier / clk / clk-pxs2.c

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index 76bf856c9e998f0a8aa076ac14cae1dc45553651..9775127650a72e8c56fc9fa2cf7af243b8ed9406 100644 (file)
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
@@ -15,7 +16,7 @@ void uniphier_pxs2_clk_init(void)
 
        /* deassert reset */
        tmp = readl(SC_RSTCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH
@@ -27,17 +28,21 @@ void uniphier_pxs2_clk_init(void)
        writel(tmp, SC_RSTCTRL);
        readl(SC_RSTCTRL); /* dummy read */
 
-#ifdef CONFIG_USB_XHCI_UNIPHIER
+#ifdef CONFIG_USB_DWC3_UNIPHIER
        tmp = readl(SC_RSTCTRL2);
        tmp |= SC_RSTCTRL2_NRST_USB3B1;
        writel(tmp, SC_RSTCTRL2);
        readl(SC_RSTCTRL2); /* dummy read */
+
+       tmp = readl(SC_RSTCTRL6);
+       tmp |= 0x37;
+       writel(tmp, SC_RSTCTRL6);
 #endif
 
        /* provide clocks */
        tmp = readl(SC_CLKCTRL);
-#ifdef CONFIG_USB_XHCI_UNIPHIER
-       tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+#ifdef CONFIG_USB_DWC3_UNIPHIER
+       tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
                SC_CLKCTRL_CEN_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH