ARM: uniphier: rename variable for DRAM controller base address

[people/ms/u-boot.git] / arch / arm / mach-uniphier / dram / umc-ph1-ld4.c

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
index 0eb47d73d7a39d35bb82af02bc2e72e6650695cd..72447cc77651eaacafdc51f1d65af0abfbd52bfb 100644 (file)
--- a/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-ld4.c
@@ -8,6 +8,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/sizes.h>
+#include <asm/processor.h>
 
 #include "../init.h"
 #include "ddrphy-regs.h"
@@ -75,7 +76,7 @@ static void umc_start_ssif(void __iomem *ssif_base)
        writel(0x00000001, ssif_base + UMC_DMDRST);
 }
 
-static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
                             int freq, unsigned long size, bool ddr3plus)
 {
        enum dram_freq freq_e;
@@ -112,29 +113,29 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
                return -EINVAL;
        }
 
-       writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA);
-       writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB);
-       writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
-       writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
-       writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
-       writel(0x04060806, dramcont + UMC_WDATACTL_D0);
-       writel(0x04a02000, dramcont + UMC_DATASET);
+       writel(umc_cmdctla_plus[freq_e], dc_base + UMC_CMDCTLA);
+       writel(umc_cmdctlb_plus[freq_e], dc_base + UMC_CMDCTLB);
+       writel(umc_spcctla[freq_e][size_e], dc_base + UMC_SPCCTLA);
+       writel(umc_spcctlb[freq_e], dc_base + UMC_SPCCTLB);
+       writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+       writel(0x04060806, dc_base + UMC_WDATACTL_D0);
+       writel(0x04a02000, dc_base + UMC_DATASET);
        writel(0x00000000, ca_base + 0x2300);
-       writel(0x00400020, dramcont + UMC_DCCGCTL);
-       writel(0x00000003, dramcont + 0x7000);
-       writel(0x0000000f, dramcont + 0x8000);
-       writel(0x000000c3, dramcont + 0x8004);
-       writel(0x00000071, dramcont + 0x8008);
-       writel(0x0000003b, dramcont + UMC_DICGCTLA);
-       writel(0x020a0808, dramcont + UMC_DICGCTLB);
-       writel(0x00000004, dramcont + UMC_FLOWCTLG);
+       writel(0x00400020, dc_base + UMC_DCCGCTL);
+       writel(0x00000003, dc_base + 0x7000);
+       writel(0x0000000f, dc_base + 0x8000);
+       writel(0x000000c3, dc_base + 0x8004);
+       writel(0x00000071, dc_base + 0x8008);
+       writel(0x0000003b, dc_base + UMC_DICGCTLA);
+       writel(0x020a0808, dc_base + UMC_DICGCTLB);
+       writel(0x00000004, dc_base + UMC_FLOWCTLG);
        writel(0x80000201, ca_base + 0xc20);
-       writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
-       writel(0x00200000, dramcont + UMC_FLOWCTLB);
-       writel(0x00004444, dramcont + UMC_FLOWCTLC);
-       writel(0x200a0a00, dramcont + UMC_SPCSETB);
-       writel(0x00000000, dramcont + UMC_SPCSETD);
-       writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
+       writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
+       writel(0x00200000, dc_base + UMC_FLOWCTLB);
+       writel(0x00004444, dc_base + UMC_FLOWCTLC);
+       writel(0x200a0a00, dc_base + UMC_SPCSETB);
+       writel(0x00000000, dc_base + UMC_SPCSETD);
+       writel(0x00000520, dc_base + UMC_DFICUPDCTLA);
 
        return 0;
 }
@@ -145,8 +146,9 @@ static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
        void __iomem *phy_base = dc_base + 0x00001000;
        int ret;
 
-       umc_dram_init_start(dc_base);
-       umc_dram_init_poll(dc_base);
+       writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
+       while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+               cpu_relax();
 
        writel(0x00000101, dc_base + UMC_DIOCTLA);