Merge branch 'master' of git://git.denx.de/u-boot-ubi

[people/ms/u-boot.git] / arch / mips / lib / cache_init.S

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 04a36b2528849459ed62f9094db4137d4d4799cb..bc8ab27b58d92289088b8659d0ac224babdb6d46 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -54,24 +54,24 @@
        mfc0    $1, CP0_CONFIG, 1
 
        /* detect line size */
-       srl     \line_sz, $1, \off + MIPS_CONF1_DL_SHIFT - MIPS_CONF1_DA_SHIFT
-       andi    \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
+       srl     \line_sz, $1, \off + MIPS_CONF1_DL_SHF - MIPS_CONF1_DA_SHF
+       andi    \line_sz, \line_sz, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHF)
        move    \sz, zero
        beqz    \line_sz, 10f
        li      \sz, 2
        sllv    \line_sz, \sz, \line_sz
 
        /* detect associativity */
-       srl     \sz, $1, \off + MIPS_CONF1_DA_SHIFT - MIPS_CONF1_DA_SHIFT
-       andi    \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
-       addi    \sz, \sz, 1
+       srl     \sz, $1, \off + MIPS_CONF1_DA_SHF - MIPS_CONF1_DA_SHF
+       andi    \sz, \sz, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHF)
+       addiu   \sz, \sz, 1
 
        /* sz *= line_sz */
        mul     \sz, \sz, \line_sz
 
        /* detect log32(sets) */
-       srl     $1, $1, \off + MIPS_CONF1_DS_SHIFT - MIPS_CONF1_DA_SHIFT
-       andi    $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
+       srl     $1, $1, \off + MIPS_CONF1_DS_SHF - MIPS_CONF1_DA_SHF
+       andi    $1, $1, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHF)
        addiu   $1, $1, 1
        andi    $1, $1, 0x7
 
@@ -99,24 +99,24 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t2, CONFIG_SYS_ICACHE_SIZE
-       li      t8, CONFIG_SYS_CACHELINE_SIZE
+       li      t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
-       l1_info t2, t8, MIPS_CONF1_IA_SHIFT
+       l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t3, CONFIG_SYS_DCACHE_SIZE
-       li      t9, CONFIG_SYS_CACHELINE_SIZE
+       li      t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
-       l1_info t3, t9, MIPS_CONF1_DA_SHIFT
+       l1_info t3, t9, MIPS_CONF1_DA_SHF
 #endif
 
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
        /* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
        li      v0, CONFIG_SYS_ICACHE_SIZE
 #else
@@ -138,6 +138,14 @@ LEAF(mips_cache_reset)
 
 #endif /* CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD */
 
+       /*
+        * The TagLo registers used depend upon the CPU implementation, but the
+        * architecture requires that it is safe for software to write to both
+        * TagLo selects 0 & 2 covering supported cases.
+        */
+       mtc0            zero, CP0_TAGLO
+       mtc0            zero, CP0_TAGLO, 2
+
        /*
         * The caches are probably in an indeterminate state, so we force good
         * parity into them by doing an invalidate for each line. If
@@ -151,7 +159,6 @@ LEAF(mips_cache_reset)
         * Initialize the I-cache first,
         */
        blez            t2, 1f
-       mtc0            zero, CP0_TAGLO
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, t2
        /* clear tag to invalidate */
@@ -169,7 +176,6 @@ LEAF(mips_cache_reset)
         * then initialize D-cache.
         */
 1:     blez            t3, 3f
-       mtc0            zero, CP0_TAGLO
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, t3
        /* clear all tags */