]> git.ipfire.org Git - people/ms/u-boot.git/blobdiff - arch/powerpc/cpu/mpc85xx/Kconfig
powerpc: mpc85xx: Convert CONFIG_SYS_CCSRBAR_DEFAULT to Kconfig option
[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / Kconfig
index 62c0dec48a0c09f84d0286e6337b4461fce9cd43..1d2e027b783e7c0ac3d06e6498d5e6b53fe8e51a 100644 (file)
@@ -16,8 +16,15 @@ config TARGET_SOCRATES
        bool "Support socrates"
        select ARCH_MPC8544
 
+config TARGET_B4420QDS
+       bool "Support B4420QDS"
+       select ARCH_B4420
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
 config TARGET_B4860QDS
        bool "Support B4860QDS"
+       select ARCH_B4860
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -41,18 +48,22 @@ config TARGET_C29XPCIE
 config TARGET_P3041DS
        bool "Support P3041DS"
        select PHYS_64BIT
+       select ARCH_P3041
 
 config TARGET_P4080DS
        bool "Support P4080DS"
        select PHYS_64BIT
+       select ARCH_P4080
 
 config TARGET_P5020DS
        bool "Support P5020DS"
        select PHYS_64BIT
+       select ARCH_P5020
 
 config TARGET_P5040DS
        bool "Support P5040DS"
        select PHYS_64BIT
+       select ARCH_P5040
 
 config TARGET_MPC8536DS
        bool "Support MPC8536DS"
@@ -156,59 +167,120 @@ config TARGET_P1025RDB
        bool "Support P1025RDB"
        select SUPPORT_SPL
        select SUPPORT_TPL
+       select ARCH_P1025
 
 config TARGET_P2020RDB
        bool "Support P2020RDB-PC"
        select SUPPORT_SPL
        select SUPPORT_TPL
+       select ARCH_P2020
 
 config TARGET_P1_TWR
        bool "Support p1_twr"
+       select ARCH_P1025
 
 config TARGET_P2041RDB
        bool "Support P2041RDB"
+       select ARCH_P2041
        select PHYS_64BIT
 
 config TARGET_QEMU_PPCE500
        bool "Support qemu-ppce500"
+       select ARCH_QEMU_E500
        select PHYS_64BIT
 
-config TARGET_T102XQDS
-       bool "Support T102xQDS"
+config TARGET_T1024QDS
+       bool "Support T1024QDS"
+       select ARCH_T1024
        select SUPPORT_SPL
        select PHYS_64BIT
 
-config TARGET_T102XRDB
-       bool "Support T102xRDB"
+config TARGET_T1023RDB
+       bool "Support T1023RDB"
+       select ARCH_T1023
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T1024RDB
+       bool "Support T1024RDB"
+       select ARCH_T1024
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T1040QDS
        bool "Support T1040QDS"
+       select ARCH_T1040
+       select PHYS_64BIT
+
+config TARGET_T1040RDB
+       bool "Support T1040RDB"
+       select ARCH_T1040
+       select SUPPORT_SPL
        select PHYS_64BIT
 
-config TARGET_T104XRDB
-       bool "Support T104xRDB"
+config TARGET_T1040D4RDB
+       bool "Support T1040D4RDB"
+       select ARCH_T1040
        select SUPPORT_SPL
        select PHYS_64BIT
 
-config TARGET_T208XQDS
-       bool "Support T208xQDS"
+config TARGET_T1042RDB
+       bool "Support T1042RDB"
+       select ARCH_T1042
        select SUPPORT_SPL
        select PHYS_64BIT
 
-config TARGET_T208XRDB
-       bool "Support T208xRDB"
+config TARGET_T1042D4RDB
+       bool "Support T1042D4RDB"
+       select ARCH_T1042
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T1042RDB_PI
+       bool "Support T1042RDB_PI"
+       select ARCH_T1042
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T2080QDS
+       bool "Support T2080QDS"
+       select ARCH_T2080
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T2080RDB
+       bool "Support T2080RDB"
+       select ARCH_T2080
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T2081QDS
+       bool "Support T2081QDS"
+       select ARCH_T2081
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T4160QDS
+       bool "Support T4160QDS"
+       select ARCH_T4160
+       select SUPPORT_SPL
+       select PHYS_64BIT
+
+config TARGET_T4160RDB
+       bool "Support T4160RDB"
+       select ARCH_T4160
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T4240QDS
        bool "Support T4240QDS"
+       select ARCH_T4240
        select SUPPORT_SPL
        select PHYS_64BIT
 
 config TARGET_T4240RDB
        bool "Support T4240RDB"
+       select ARCH_T4240
        select SUPPORT_SPL
        select PHYS_64BIT
 
@@ -218,6 +290,7 @@ config TARGET_CONTROLCENTERD
 
 config TARGET_KMP204X
        bool "Support kmp204x"
+       select ARCH_P2041
        select PHYS_64BIT
 
 config TARGET_XPEDITE520X
@@ -230,17 +303,30 @@ config TARGET_XPEDITE537X
 
 config TARGET_XPEDITE550X
        bool "Support xpedite550x"
+       select ARCH_P2020
 
 config TARGET_UCP1020
        bool "Support uCP1020"
        select ARCH_P1020
 
-config TARGET_CYRUS
-       bool "Support Varisys Cyrus"
+config TARGET_CYRUS_P5020
+       bool "Support Varisys Cyrus P5020"
+       select ARCH_P5020
+       select PHYS_64BIT
+
+config TARGET_CYRUS_P5040
+        bool "Support Varisys Cyrus P5040"
+       select ARCH_P5040
        select PHYS_64BIT
 
 endchoice
 
+config ARCH_B4420
+       bool
+
+config ARCH_B4860
+       bool
+
 config ARCH_BSC9131
        bool
 
@@ -301,6 +387,140 @@ config ARCH_P1023
 config ARCH_P1024
        bool
 
+config ARCH_P1025
+       bool
+
+config ARCH_P2020
+       bool
+
+config ARCH_P2041
+       bool
+
+config ARCH_P3041
+       bool
+
+config ARCH_P4080
+       bool
+
+config ARCH_P5020
+       bool
+
+config ARCH_P5040
+       bool
+
+config ARCH_QEMU_E500
+       bool
+
+config ARCH_T1023
+       bool
+
+config ARCH_T1024
+       bool
+
+config ARCH_T1040
+       bool
+
+config ARCH_T1042
+       bool
+
+config ARCH_T2080
+       bool
+
+config ARCH_T2081
+       bool
+
+config ARCH_T4160
+       bool
+
+config ARCH_T4240
+       bool
+
+config MAX_CPUS
+       int "Maximum number of CPUs permitted for MPC85xx"
+       default 12 if ARCH_T4240
+       default 8 if ARCH_P4080 || \
+                    ARCH_T4160
+       default 4 if ARCH_B4860 || \
+                    ARCH_P2041 || \
+                    ARCH_P3041 || \
+                    ARCH_P5040 || \
+                    ARCH_T1040 || \
+                    ARCH_T1042 || \
+                    ARCH_T2080 || \
+                    ARCH_T2081
+       default 2 if ARCH_B4420 || \
+                    ARCH_BSC9132 || \
+                    ARCH_MPC8572 || \
+                    ARCH_P1020 || \
+                    ARCH_P1021 || \
+                    ARCH_P1022 || \
+                    ARCH_P1023 || \
+                    ARCH_P1024 || \
+                    ARCH_P1025 || \
+                    ARCH_P2020 || \
+                    ARCH_P5020 || \
+                    ARCH_T1020 || \
+                    ARCH_T1022 || \
+                    ARCH_T1023 || \
+                    ARCH_T1024
+       default 1
+       help
+         Set this number to the maximum number of possible CPUs in the SoC.
+         SoCs may have multiple clusters with each cluster may have multiple
+         ports. If some ports are reserved but higher ports are used for
+         cores, count the reserved ports. This will allocate enough memory
+         in spin table to properly handle all cores.
+
+config SYS_CCSRBAR_DEFAULT
+       hex "Default CCSRBAR address"
+       default 0xff700000 if   ARCH_BSC9131    || \
+                               ARCH_BSC9132    || \
+                               ARCH_C29X       || \
+                               ARCH_MPC8536    || \
+                               ARCH_MPC8540    || \
+                               ARCH_MPC8541    || \
+                               ARCH_MPC8544    || \
+                               ARCH_MPC8548    || \
+                               ARCH_MPC8555    || \
+                               ARCH_MPC8560    || \
+                               ARCH_MPC8568    || \
+                               ARCH_MPC8569    || \
+                               ARCH_MPC8572    || \
+                               ARCH_P1010      || \
+                               ARCH_P1011      || \
+                               ARCH_P1020      || \
+                               ARCH_P1021      || \
+                               ARCH_P1022      || \
+                               ARCH_P1024      || \
+                               ARCH_P1025      || \
+                               ARCH_P2020
+       default 0xff600000 if   ARCH_P1023
+       default 0xfe000000 if   ARCH_B4420      || \
+                               ARCH_B4860      || \
+                               ARCH_P2041      || \
+                               ARCH_P3041      || \
+                               ARCH_P4080      || \
+                               ARCH_P5020      || \
+                               ARCH_P5040      || \
+                               ARCH_T1013      || \
+                               ARCH_T1014      || \
+                               ARCH_T1020      || \
+                               ARCH_T1022      || \
+                               ARCH_T1023      || \
+                               ARCH_T1024      || \
+                               ARCH_T1040      || \
+                               ARCH_T1042      || \
+                               ARCH_T2080      || \
+                               ARCH_T2081      || \
+                               ARCH_T4160      || \
+                               ARCH_T4240
+       default 0xe0000000 if ARCH_QEMU_E500
+       help
+               Default value of CCSRBAR comes from power-on-reset. It
+               is fixed on each SoC. Some SoCs can have different value
+               if changed by pre-boot regime. The value here must match
+               the current value in SoC. If not sure, do not change.
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"