powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081

[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 321ade24fe7d639f1723f2bcb8672167202167c4..4de5dcfad05e3393697333317ecddb3749bb2b6d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -73,7 +73,8 @@ void get_sys_info(sys_info_t *sys_info)
                [14] = 4,       /* CC4 PPL / 4 */
        };
        uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
-#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
+#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
+       defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
        uint rcw_tmp;
 #endif
        uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
@@ -130,7 +131,8 @@ void get_sys_info(sys_info_t *sys_info)
         * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
         */
 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
-       defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
+       defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
+       defined(CONFIG_ARCH_T2081)
        svr = get_svr();
        switch (SVR_SOC_VER(svr)) {
        case SVR_T4240:
@@ -200,11 +202,11 @@ void get_sys_info(sys_info_t *sys_info)
        }
 #endif
 
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
-       defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
+       defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 #define FM1_CLK_SEL    0xe0000000
 #define FM1_CLK_SHIFT  29
-#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define FM1_CLK_SEL    0x00000007
 #define FM1_CLK_SHIFT  0
 #else
@@ -214,7 +216,7 @@ void get_sys_info(sys_info_t *sys_info)
 #define FM1_CLK_SHIFT  26
 #endif
 #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
-#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
+#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
        rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
 #else
        rcw_tmp = in_be32(&gur->rcwsr[7]);
@@ -453,6 +455,48 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 #endif
 
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#if defined(CONFIG_ARCH_T2080)
+#define ESDHC_CLK_SEL  0x00000007
+#define ESDHC_CLK_SHIFT        0
+#define ESDHC_CLK_RCWSR        15
+#else  /* Support T1040 T1024 by now */
+#define ESDHC_CLK_SEL  0xe0000000
+#define ESDHC_CLK_SHIFT        29
+#define ESDHC_CLK_RCWSR        7
+#endif
+       rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
+       switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
+       case 1:
+               sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
+               break;
+       case 2:
+               sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
+               break;
+       case 3:
+               sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
+               break;
+#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
+       case 4:
+               sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
+               break;
+#if defined(CONFIG_ARCH_T2080)
+       case 5:
+               sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
+               break;
+#endif
+       case 6:
+               sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
+               break;
+       case 7:
+               sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
+               break;
+#endif
+       default:
+               sys_info->freq_sdhc = 0;
+               printf("Error: Unknown SDHC peripheral clock select!\n");
+       }
+#endif
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
        for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -552,7 +596,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #ifdef CONFIG_QE
-#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
        sys_info->freq_qe =  sys_info->freq_systembus;
 #else
        qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
@@ -581,8 +625,8 @@ void get_sys_info(sys_info_t *sys_info)
                 * for four times the clock divider values.
                 */
                lcrr_div *= 4;
-#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
-    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
+#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \
+       !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560)
                /*
                 * Yes, the entire PQ38 family use the same
                 * bit-representation for twice the clock divider values.
@@ -608,7 +652,7 @@ void get_sys_info(sys_info_t *sys_info)
 int get_clocks (void)
 {
        sys_info_t sys_info;
-#ifdef CONFIG_MPC8544
+#ifdef CONFIG_ARCH_MPC8544
        volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
 #endif
 #if defined(CONFIG_CPM2)
@@ -637,11 +681,11 @@ int get_clocks (void)
         * for that SOC. This information is taken from application note
         * AN2919.
         */
-#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
-       defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
-       defined(CONFIG_P1022)
+#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8541) || \
+       defined(CONFIG_ARCH_MPC8560) || defined(CONFIG_ARCH_MPC8555) || \
+       defined(CONFIG_ARCH_P1022)
        gd->arch.i2c1_clk = sys_info.freq_systembus;
-#elif defined(CONFIG_MPC8544)
+#elif defined(CONFIG_ARCH_MPC8544)
        /*
         * On the 8544, the I2C clock is the same as the SEC clock.  This can be
         * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
@@ -660,12 +704,15 @@ int get_clocks (void)
        gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
-       defined(CONFIG_P1014)
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+       gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
+#else
+#if defined(CONFIG_ARCH_MPC8569) || defined(CONFIG_ARCH_P1010)
        gd->arch.sdhc_clk = gd->bus_clk;
 #else
        gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
+#endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)