PowerPC: Don't destroy fixup table while doing fixups

[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / start.S

diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 4bad32f9f57689056f2fb06b39d8c04df53c0c7d..65195f528a8d7c884f2531cef1760d14e5062e0c 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -63,8 +63,9 @@
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
  */
+#include <asm-offsets.h>
 #include <config.h>
-#include <ppc4xx.h>
+#include <asm/ppc4xx.h>
 #include <timestamp.h>
 #include <version.h>
 
@@ -182,8 +183,8 @@
 # endif
 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
 
-#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
-#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
+#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
+#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
 #endif
 
 /*
@@ -261,6 +262,7 @@
        GET_GOT
        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
        bl      board_init_f
+       /* NOTREACHED - board_init_f() does not return */
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT)
@@ -340,6 +342,9 @@ _start_440:
        mfspr   r1,SPRN_DBCR0
        andis.  r1, r1, 0x8000  /* test DBCR0[EDM] bit                  */
        bne     skip_debug_init /* if set, don't clear debug register   */
+       mfspr   r1,SPRN_CCR0
+       ori     r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
+       mtspr   SPRN_CCR0,r1
        mtspr   SPRN_DBCR0,r0
        mtspr   SPRN_DBCR1,r0
        mtspr   SPRN_DBCR2,r0
@@ -652,8 +657,8 @@ _start:
        /* Clear Dcache to use as RAM */
        addis   r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
        ori     r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
-       addis   r4,r0,CONFIG_SYS_INIT_RAM_END@h
-       ori     r4,r4,CONFIG_SYS_INIT_RAM_END@l
+       addis   r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
+       ori     r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
        rlwinm. r5,r4,0,27,31
        rlwinm  r5,r4,27,5,31
        beq     ..d_ran
@@ -700,7 +705,8 @@ _start:
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460SX)
        mtdcr   L2_CACHE_CFG,r0         /* Ensure L2 Cache is off */
-#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+      defined(CONFIG_APM821XX)
        lis     r1, 0x0000
        ori     r1,r1,0x0008            /* Set L2_CACHE_CFG[RDBW]=1 */
        mtdcr   L2_CACHE_CFG,r1
@@ -728,7 +734,8 @@ _start:
        lis     r1, 0x8003
        ori     r1,r1, 0x0980           /* fourth 64k */
        mtdcr   ISRAM0_SB3CR,r1
-#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
+      defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
        lis     r1,0x0000               /* BAS = X_0000_0000 */
        ori     r1,r1,0x0984            /* first 64k */
        mtdcr   ISRAM0_SB0CR,r1
@@ -741,7 +748,8 @@ _start:
        lis     r1, 0x0003
        ori     r1,r1, 0x0984           /* fourth 64k */
        mtdcr   ISRAM0_SB3CR,r1
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+    defined(CONFIG_APM821XX)
        lis     r2,0x7fff
        ori     r2,r2,0xffff
        mfdcr   r1,ISRAM1_DPC
@@ -752,7 +760,7 @@ _start:
        mtdcr   ISRAM1_PMEG,r1
 
        lis     r1,0x0004               /* BAS = 4_0004_0000 */
-       ori     r1,r1,0x0984            /* 64k */
+       ori     r1,r1,ISRAM1_SIZE       /* ocm size */
        mtdcr   ISRAM1_SB0CR,r1
 #endif
 #elif defined(CONFIG_460SX)
@@ -797,6 +805,7 @@ _start:
 
        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
        bl      board_init_f
+       /* NOTREACHED - board_init_f() does not return */
 #endif
 
 #endif /* CONFIG_440 */
@@ -905,6 +914,7 @@ _start:
        GET_GOT                 /* initialize GOT access                        */
 
        bl      board_init_f    /* run first part of init code (from Flash)     */
+       /* NOTREACHED - board_init_f() does not return */
 
 #endif /* CONFIG_IOP480 */
 
@@ -1082,8 +1092,8 @@ _start:
        lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
        ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-       lis     r4, CONFIG_SYS_INIT_RAM_END@h
-       ori     r4, r4, CONFIG_SYS_INIT_RAM_END@l
+       lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
+       ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
 
        /*
         * Convert the size, in bytes, to the number of cache lines/blocks
@@ -1110,12 +1120,12 @@ _start:
        lis     r1, CONFIG_SYS_INIT_RAM_ADDR@h
        ori     r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
-       lis     r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
-       ori     r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
+       lis     r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
+       ori     r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
        mtctr   r4
 
        lis     r2, CONFIG_SYS_INIT_RAM_ADDR@h
-       ori     r2, r2, CONFIG_SYS_INIT_RAM_END@l
+       ori     r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
 
        lis     r4, CONFIG_SYS_INIT_RAM_PATTERN@h
        ori     r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
@@ -1174,8 +1184,9 @@ _start:
 
        bl      cpu_init_f      /* run low-level CPU init code     (from Flash) */
 
-       /* NEVER RETURNS! */
        bl      board_init_f    /* run first part of init code (from Flash)     */
+       /* NOTREACHED - board_init_f() does not return */
+
 #endif /* CONFIG_NAND_SPL */
 
 #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
@@ -1389,7 +1400,7 @@ relocate_code:
 
        /* Flush initial global data range */
        mr      r3, r4
-       addi    r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
+       addi    r4, r4, GENERATED_GBL_DATA_SIZE@l
        bl      flush_dcache_range
 
 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
@@ -1404,8 +1415,8 @@ relocate_code:
        lis     r3, CONFIG_SYS_INIT_RAM_ADDR@h
        ori     r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
 
-       lis     r4, CONFIG_SYS_INIT_RAM_END@h
-       ori     r4, r4, CONFIG_SYS_INIT_RAM_END@l
+       lis     r4, CONFIG_SYS_INIT_RAM_SIZE@h
+       ori     r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
        add     r4, r4, r3
 
        bl      invalidate_dcache_range
@@ -1598,10 +1609,12 @@ in_ram:
        beq     4f
 3:     lwzu    r4,4(r3)
        lwzux   r0,r4,r11
+       cmpwi   r0,0
        add     r0,r0,r11
-       stw     r10,0(r3)
+       stw     r4,0(r3)
+       beq-    5f
        stw     r0,0(r4)
-       bdnz    3b
+5:     bdnz    3b
 4:
 clear_bss:
        /*