Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[people/ms/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c3a37600d323bceb033e09c25b913cb5ba6dcb5e..e1fc0f72c06a65e0ece92beb27443da49ccc26b7 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -368,6 +368,7 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 #define CONFIG_SYS_FSL_ERRATUM_A004849
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@@ -413,6 +414,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004849
 #define CONFIG_SYS_FSL_ERRATUM_A004580
 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
 #define CONFIG_SYS_PPC64               /* 64-bit core */
@@ -474,6 +476,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_A005812
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS                        1
@@ -497,6 +500,10 @@
 #define CONFIG_TSECV2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_FSL_DSP_DDR_ADDR    0x40000000
+#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
+#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
+#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT     0xff600000
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  3
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_NAND_FSL_IFC
@@ -528,6 +535,8 @@
 #endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     5
 #define CONFIG_SYS_FSL_NUM_LAWS                32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SRDS_3
 #define CONFIG_SYS_FSL_SRDS_4
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
@@ -558,6 +567,8 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2  /* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_LAWS                32
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #define CONFIG_SYS_FSL_SEC_COMPAT      4
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_4_7
@@ -619,6 +630,18 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xfe000000
 
+#elif defined(CONFIG_PPC_C29X)
+#define CONFIG_MAX_CPUS                        1
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
+#define CONFIG_TSECV2_1
+#define CONFIG_SYS_FSL_SEC_COMPAT      6
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
+
 #else
 #error Processor type not defined for this platform
 #endif