Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel...

[thirdparty/linux.git] / arch / riscv / kernel / cpufeature.c

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index e3803822ab5a3a0ee36852cd9b08f9db8ee76fdc..7aeba01dcfd408beb0cafc69a5084e38e95ed03a 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -93,10 +93,10 @@ static bool riscv_isa_extension_check(int id)
                return true;
        case RISCV_ISA_EXT_ZICBOZ:
                if (!riscv_cboz_block_size) {
-                       pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");
+                       pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n");
                        return false;
                } else if (!is_power_of_2(riscv_cboz_block_size)) {
-                       pr_err("cboz-block-size present, but is not a power-of-2\n");
+                       pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n");
                        return false;
                }
                return true;
@@ -206,10 +206,11 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc
                switch (*ext) {
                case 's':
                        /*
-                        * Workaround for invalid single-letter 's' & 'u'(QEMU).
+                        * Workaround for invalid single-letter 's' & 'u' (QEMU).
                         * No need to set the bit in riscv_isa as 's' & 'u' are
-                        * not valid ISA extensions. It works until multi-letter
-                        * extension starting with "Su" appears.
+                        * not valid ISA extensions. It works unless the first
+                        * multi-letter extension in the ISA string begins with
+                        * "Su" and is not prefixed with an underscore.
                         */
                        if (ext[-1] != '_' && ext[1] == 'u') {
                                ++isa;
@@ -655,6 +656,12 @@ static int check_unaligned_access_boot_cpu(void)
 
 arch_initcall(check_unaligned_access_boot_cpu);
 
+void riscv_user_isa_enable(void)
+{
+       if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))
+               csr_set(CSR_SENVCFG, ENVCFG_CBZE);
+}
+
 #ifdef CONFIG_RISCV_ALTERNATIVE
 /*
  * Alternative patch sites consider 48 bits when determining when to patch