Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel...

[thirdparty/linux.git] / arch / riscv / mm / fault.c

diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index fd7662afddeacf037a2de04acb094820dedf1022..3e2708c626a854884358ced1e6f60bbd1e5f5fa6 100644 (file)
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -16,6 +16,7 @@
 
 #include <asm/pgalloc.h>
 #include <asm/ptrace.h>
+#include <asm/tlbflush.h>
 
 /*
  * This routine handles page faults.  It determines the address and the
@@ -265,6 +266,18 @@ vmalloc_fault:
                pte_k = pte_offset_kernel(pmd_k, addr);
                if (!pte_present(*pte_k))
                        goto no_context;
+
+               /*
+                * The kernel assumes that TLBs don't cache invalid
+                * entries, but in RISC-V, SFENCE.VMA specifies an
+                * ordering constraint, not a cache flush; it is
+                * necessary even after writing invalid entries.
+                * Relying on flush_tlb_fix_spurious_fault would
+                * suffice, but the extra traps reduce
+                * performance. So, eagerly SFENCE.VMA.
+                */
+               local_flush_tlb_page(addr);
+
                return;
        }
 }