+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
#include <mmc.h>
+#include <asm/cache.h>
#include <asm/io.h>
+#include <asm/ioapic.h>
#include <asm/irq.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/post.h>
-#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
-static struct pci_device_id mmc_supported[] = {
- { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
- {},
-};
-
-/*
- * TODO:
- *
- * This whole routine should be removed until we fully convert the ICH SPI
- * driver to DM and make use of DT to pass the bios control register offset
- */
-static void unprotect_spi_flash(void)
-{
- u32 bc;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, &bc);
- bc |= 0x1; /* unprotect the flash */
- qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
-}
-
static void quark_setup_mtrr(void)
{
u32 base, mask;
/* Turn on legacy segments (A/B/E/F) decode to system RAM */
quark_enable_legacy_seg();
- unprotect_spi_flash();
-
return 0;
}
return 0;
}
-int print_cpuinfo(void)
+int checkcpu(void)
{
- post_code(POST_CPU_INFO);
- return default_print_cpuinfo();
+ return 0;
}
-void reset_cpu(ulong addr)
+int print_cpuinfo(void)
{
- /* cold reset */
- x86_full_reset();
+ post_code(POST_CPU_INFO);
+ return default_print_cpuinfo();
}
static void quark_pcie_init(void)
writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
}
-int arch_early_init_r(void)
-{
- quark_pcie_init();
-
- quark_usb_init();
-
- return 0;
-}
-
-int cpu_mmc_init(bd_t *bis)
-{
- return pci_mmc_init("Quark SDHCI", mmc_supported);
-}
-
-void cpu_irq_init(void)
+static void quark_irq_init(void)
{
struct quark_rcba *rcba;
u32 base;
&rcba->d20d21_ir);
}
+int arch_early_init_r(void)
+{
+ quark_pcie_init();
+
+ quark_usb_init();
+
+ quark_irq_init();
+
+ return 0;
+}
+
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
mrccache_save();
#endif
+ /* Assign a unique I/O APIC ID */
+ io_apic_set_id(1);
+
return 0;
}
return;
}
-
-int reserve_arch(void)
-{
-#ifdef CONFIG_ENABLE_MRC_CACHE
- return mrccache_reserve();
-#else
- return 0;
-#endif
-}