x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer

[people/ms/u-boot.git] / arch / x86 / dts / minnowmax.dts

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 936455b5e55ada3aff85dfd0b61dbf6ebd4fe3b9..4c0a8fe26f2df8ee2b20788cdd4e5f81d423fa94 100644 (file)
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 
+#include <asm/arch-baytrail/fsp/fsp_configs.h>
 #include <dt-bindings/gpio/x86-gpio.h>
 #include <dt-bindings/interrupt-router/intel-irq.h>
 
@@ -13,6 +14,7 @@
 /include/ "serial.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
 
 / {
        model = "Intel Minnowboard Max";
@@ -29,11 +31,11 @@
 
        pch_pinctrl {
                compatible = "intel,x86-pinctrl";
+               reg = <0 0>;
 
                /* GPIO E0 */
                soc_gpio_s5_0@0 {
                        gpio-offset = <0x80 0>;
-                       pad-offset = <0x1d0>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -42,7 +44,6 @@
                /* GPIO E1 */
                soc_gpio_s5_1@0 {
                        gpio-offset = <0x80 1>;
-                       pad-offset = <0x210>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -51,7 +52,6 @@
                /* GPIO E2 */
                soc_gpio_s5_2@0 {
                        gpio-offset = <0x80 2>;
-                       pad-offset = <0x1e0>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -59,7 +59,6 @@
 
                pin_usb_host_en0@0 {
                        gpio-offset = <0x80 8>;
-                       pad-offset = <0x260>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;
@@ -67,11 +66,25 @@
 
                pin_usb_host_en1@0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;
                };
+
+               /*
+                * As of today, the latest version FSP (gold4) for BayTrail
+                * misses the PAD configuration of the SD controller's Card
+                * Detect signal. The default PAD value for the CD pin sets
+                * the pin to work in GPIO mode, which causes card detect
+                * status cannot be reflected by the Present State register
+                * in the SD controller (bit 16 & bit 18 are always zero).
+                *
+                * Configure this pin to function 1 (SD controller).
+                */
+               sdmmc3_cd@0 {
+                       pad-offset = <0x3a0>;
+                       mode-func = <1>;
+               };
        };
 
        chosen {
@@ -201,6 +214,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0 0x20>;
                                bank-name = "A";
+                               use-lvl-write-cache;
                        };
 
                        gpiob {
@@ -208,6 +222,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x20 0x20>;
                                bank-name = "B";
+                               use-lvl-write-cache;
                        };
 
                        gpioc {
@@ -215,6 +230,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x40 0x20>;
                                bank-name = "C";
+                               use-lvl-write-cache;
                        };
 
                        gpiod {
@@ -222,6 +238,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x60 0x20>;
                                bank-name = "D";
+                               use-lvl-write-cache;
                        };
 
                        gpioe {
@@ -229,6 +246,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x80 0x20>;
                                bank-name = "E";
+                               use-lvl-write-cache;
                        };
 
                        gpiof {
@@ -236,25 +254,26 @@
                                u-boot,dm-pre-reloc;
                                reg = <0xA0 0x20>;
                                bank-name = "F";
+                               use-lvl-write-cache;
                        };
                };
        };
 
        fsp {
                compatible = "intel,baytrail-fsp";
-               fsp,mrc-init-tseg-size = <0>;
-               fsp,mrc-init-mmio-size = <0x800>;
+               fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
+               fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
                fsp,mrc-init-spd-addr1 = <0xa0>;
                fsp,mrc-init-spd-addr2 = <0xa2>;
-               fsp,emmc-boot-mode = <2>;
+               fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
                fsp,enable-sdio;
                fsp,enable-sdcard;
                fsp,enable-hsuart1;
                fsp,enable-spi;
                fsp,enable-sata;
-               fsp,sata-mode = <1>;
-               fsp,enable-lpe;
-               fsp,lpss-sio-enable-pci-mode;
+               fsp,sata-mode = <SATA_MODE_AHCI>;
+               fsp,lpe-mode = <LPE_MODE_PCI>;
+               fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
                fsp,enable-dma0;
                fsp,enable-dma1;
                fsp,enable-i2c0;
@@ -266,26 +285,24 @@
                fsp,enable-i2c6;
                fsp,enable-pwm0;
                fsp,enable-pwm1;
-               fsp,igd-dvmt50-pre-alloc = <2>;
-               fsp,aperture-size = <2>;
-               fsp,gtt-size = <2>;
-               fsp,serial-debug-port-address = <0x3f8>;
-               fsp,serial-debug-port-type = <1>;
-               fsp,scc-enable-pci-mode;
-               fsp,os-selection = <4>;
+               fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
+               fsp,aperture-size = <APERTURE_SIZE_256MB>;
+               fsp,gtt-size = <GTT_SIZE_2MB>;
+               fsp,scc-mode = <SCC_MODE_PCI>;
+               fsp,os-selection = <OS_SELECTION_LINUX>;
                fsp,emmc45-ddr50-enabled;
                fsp,emmc45-retune-timer-value = <8>;
                fsp,enable-igd;
                fsp,enable-memory-down;
                fsp,memory-down-params {
                        compatible = "intel,baytrail-fsp-mdp";
-                       fsp,dram-speed = <1>;
-                       fsp,dram-type = <1>;
+                       fsp,dram-speed = <DRAM_SPEED_1066MTS>;
+                       fsp,dram-type = <DRAM_TYPE_DDR3L>;
                        fsp,dimm-0-enable;
-                       fsp,dimm-width = <1>;
-                       fsp,dimm-density = <2>;
-                       fsp,dimm-bus-width = <3>;
-                       fsp,dimm-sides = <0>;
+                       fsp,dimm-width = <DIMM_WIDTH_X16>;
+                       fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
+                       fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
+                       fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
                        fsp,dimm-tcl = <0xb>;
                        fsp,dimm-trpt-rcd = <0xb>;
                        fsp,dimm-twr = <0xc>;