rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 50771879e1b21ce762cb250565125375f37eaef4..febc61a0869d7e2d0ea76448c298d1c1df1899ec 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -453,7 +453,7 @@ int checkboard(void)
 }
 
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
        long dram_size;
@@ -462,77 +462,10 @@ long int initdram (int board_type)
 
        return dram_size;
 #else
-       return CFG_MBYTES_SDRAM << 20;
+       return CONFIG_SYS_MBYTES_SDRAM << 20;
 #endif
 }
 
-#if defined(CFG_DRAM_TEST)
-int testdram(void)
-{
-       unsigned long *mem = (unsigned long *)0;
-       const unsigned long kend = (1024 / sizeof(unsigned long));
-       unsigned long k, n, *p32, ctr;
-       const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
-
-       mtmsr(0);
-
-       for (k = 0; k < CFG_MBYTES_SDRAM*1024;
-            ++k, mem += (1024 / sizeof(unsigned long))) {
-               if ((k & 1023) == 0) {
-                       printf("%3d MB\r", k / 1024);
-               }
-
-               memset(mem, 0xaaaaaaaa, 1024);
-               for (n = 0; n < kend; ++n) {
-                       if (mem[n] != 0xaaaaaaaa) {
-                               printf("SDRAM test fails at: %08x\n",
-                                      (uint) & mem[n]);
-                               return 1;
-                       }
-               }
-
-               memset(mem, 0x55555555, 1024);
-               for (n = 0; n < kend; ++n) {
-                       if (mem[n] != 0x55555555) {
-                               printf("SDRAM test fails at: %08x\n",
-                                      (uint) & mem[n]);
-                               return 1;
-                       }
-               }
-       }
-
-       /*
-        * Perform a sequence test to ensure that all
-        * memory locations are uniquely addressable
-        */
-       ctr = 0;
-       p32 = 0;
-       while ((unsigned long)p32 != bend) {
-               if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-                       printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
-               *p32++ = ctr++;
-       }
-
-       ctr = 0;
-       p32 = 0;
-       while ((unsigned long)p32 != bend) {
-               if (0 == ((unsigned long)p32 & ((1<<20)-1)))
-                       printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
-
-               if (*p32 != ctr) {
-                       printf("SDRAM test fails at: %08x\n", p32);
-                       return 1;
-               }
-
-               ctr++;
-               p32++;
-       }
-
-       printf("SDRAM test passes\n");
-       return 0;
-}
-#endif
-
 /*************************************************************************
  *  pci_pre_init
  *
@@ -596,7 +529,7 @@ int pci_pre_init(struct pci_controller *hose)
  *     may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
        /*--------------------------------------------------------------------------+
@@ -610,14 +543,14 @@ void pci_target_init(struct pci_controller *hose)
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
        out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 
        out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 
@@ -632,8 +565,8 @@ void pci_target_init(struct pci_controller *hose)
 
        /* Program the board's subsystem id/vendor id */
        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CFG_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
        /* Configure command register as bus master */
        pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -647,13 +580,13 @@ void pci_target_init(struct pci_controller *hose)
        pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
        unsigned short temp_short;
@@ -668,7 +601,7 @@ void pci_master_init(struct pci_controller *hose)
                              temp_short | PCI_COMMAND_MASTER |
                              PCI_COMMAND_MEMORY);
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host