*/
#include <common.h>
+#include <errno.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/ppc4xx.h>
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_SYS_NO_FLASH)
+#if defined(CONFIG_MTD_NOR_FLASH)
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
#endif
int misc_init_r(void)
{
-#if !defined(CONFIG_SYS_NO_FLASH)
+#if defined(CONFIG_MTD_NOR_FLASH)
uint pbcr;
int size_val = 0;
#endif
#endif
u32 reg;
-#if !defined(CONFIG_SYS_NO_FLASH)
+#if defined(CONFIG_MTD_NOR_FLASH)
/* Re-do flash sizing to get full correct info */
/* adjust flash start and offset */
CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
-#endif /* CONFIG_SYS_NO_FLASH */
+#endif /* CONFIG_MTD_NOR_FLASH */
/*
* USB suff...
* On NAND-booting sequoia, we need to patch the chips select numbers
* in the dtb (CS0 - NAND, CS3 - NOR)
*/
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
int len;
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NOR chip select for NAND booting\n");
- return;
+ return -FDT_ERR_NOTFOUND;
}
reg = (u32 *)&prop->data[0];
reg[0] = 3;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NOR mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NOR mappings\n");
+ return rc;
}
/* And now configure NAND chip select to 0 instead of 3 */
prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
if (prop == NULL) {
printf("Unable to update NDFC chip select for NAND booting\n");
- return;
+ return len;
}
reg = (u32 *)&prop->data[0];
reg[0] = 0;
rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
if (rc) {
- printf("Unable to update property NDFC mappings, err=%s\n",
- fdt_strerror(rc));
- return;
+ printf("Unable to update property NDFC mapping\n");
+ return rc;
}
+
+ return 0;
}
#endif /* CONFIG_SYS_RAMBOOT */