*/
#include <common.h>
+#include <dm.h>
#include <asm/io.h>
#include <asm/arch/gxbb.h>
#include <asm/arch/sm.h>
-#include <dm/platdata.h>
-#include <phy.h>
+#include <asm/arch/eth.h>
+#include <asm/arch/mem.h>
#define EFUSE_SN_OFFSET 20
#define EFUSE_SN_SIZE 16
return 0;
}
-static const struct eth_pdata gxbb_eth_pdata = {
- .iobase = GXBB_ETH_BASE,
- .phy_interface = PHY_INTERFACE_MODE_RGMII,
-};
-
-U_BOOT_DEVICE(meson_eth) = {
- .name = "eth_designware",
- .platdata = &gxbb_eth_pdata,
-};
-
int misc_init_r(void)
{
u8 mac_addr[EFUSE_MAC_SIZE];
+ char serial[EFUSE_SN_SIZE];
ssize_t len;
- /* Select Ethernet function */
- setbits_le32(GXBB_PINMUX(6), 0x3fff);
-
- /* Set RGMII mode */
- setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF |
- GXBB_ETH_REG_0_TX_PHASE(1) |
- GXBB_ETH_REG_0_TX_RATIO(4) |
- GXBB_ETH_REG_0_PHY_CLK_EN |
- GXBB_ETH_REG_0_CLK_EN);
+ meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
/* Enable power and clock gate */
- setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
- clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+ setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
/* Reset PHY on GPIOZ_14 */
clrbits_le32(GXBB_GPIO_EN(3), BIT(14));
mdelay(10);
setbits_le32(GXBB_GPIO_OUT(3), BIT(14));
- if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);
if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
- eth_setenv_enetaddr("ethaddr", mac_addr);
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ }
+
+ if (!env_get("serial#")) {
+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+ EFUSE_SN_SIZE);
+ if (len == EFUSE_SN_SIZE)
+ env_set("serial#", serial);
}
return 0;
}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ meson_gx_init_reserved_memory(blob);
+
+ return 0;
+}