* for different CPU's which may lack non-cache L1 data.
*/
#ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
# define L1_DATA_B_SRAM_SIZE 0
#endif
/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
MEMORY
{
- ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+ ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
}
board/bf533-ezkit/bf533-ezkit.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
- common/environment.o (.text)
+ common/env_embedded.o (.text)
#endif
*(.text .text.*)