#include <common.h>
#include <mpc824x.h>
#include <pci.h>
+#include <i2c.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
int checkboard (void)
{
return 0;
}
-#if 0 /* NOT USED */
+#if 0 /* NOT USED */
int checkflash (void)
{
/* TODO: XXX XXX XXX */
}
#endif
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
- int i, cnt;
- volatile uchar * base= CFG_SDRAM_BASE;
- volatile ulong * addr;
- ulong save[32];
- ulong val, ret = 0;
-
- for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
- addr = (volatile ulong *)base + cnt;
- save[i++] = *addr;
- *addr = ~cnt;
- }
-
- addr = (volatile ulong *)base;
- save[i] = *addr;
- *addr = 0;
-
- if (*addr != 0) {
- *addr = save[i];
- goto Done;
+ int m, row, col, bank, i;
+ unsigned long start, end;
+ uint32_t mccr1;
+ uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
+ uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
+ uint8_t mber = 0;
+
+ i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+
+ if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
+ m = i2c_reg_read (0x50, 5); /* # of physical banks */
+ row = i2c_reg_read (0x50, 3); /* # of rows */
+ col = i2c_reg_read (0x50, 4); /* # of columns */
+ bank = i2c_reg_read (0x50, 17); /* # of logical banks */
+
+ CONFIG_READ_WORD(MCCR1, mccr1);
+ mccr1 &= 0xffff0000;
+
+ start = CFG_SDRAM_BASE;
+ end = start + (1 << (col + row + 3) ) * bank - 1;
+
+ for (i = 0; i < m; i++) {
+ mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
+ if (i < 4) {
+ msar1 |= ((start >> 20) & 0xff) << i * 8;
+ emsar1 |= ((start >> 28) & 0xff) << i * 8;
+ mear1 |= ((end >> 20) & 0xff) << i * 8;
+ emear1 |= ((end >> 28) & 0xff) << i * 8;
+ } else {
+ msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
+ emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
+ mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
+ emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
+ }
+ mber |= 1 << i;
+ start += (1 << (col + row + 3) ) * bank;
+ end += (1 << (col + row + 3) ) * bank;
}
-
- for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
- addr = (volatile ulong *)base + cnt;
- val = *addr;
- *addr = save[--i];
- if (val != ~cnt) {
-/* ulong new_bank0_end = cnt * sizeof(long) - 1;
- ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
- ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);*/
-
- ret = cnt * sizeof(long);
- goto Done;
+ for (; i < 8; i++) {
+ if (i < 4) {
+ msar1 |= 0xff << i * 8;
+ emsar1 |= 0x30 << i * 8;
+ mear1 |= 0xff << i * 8;
+ emear1 |= 0x30 << i * 8;
+ } else {
+ msar2 |= 0xff << (i-4) * 8;
+ emsar2 |= 0x30 << (i-4) * 8;
+ mear2 |= 0xff << (i-4) * 8;
+ emear2 |= 0x30 << (i-4) * 8;
}
}
- ret = CFG_MAX_RAM_SIZE;
-Done:
- return ret;
+ CONFIG_WRITE_WORD(MCCR1, mccr1);
+ CONFIG_WRITE_WORD(MSAR1, msar1);
+ CONFIG_WRITE_WORD(EMSAR1, emsar1);
+ CONFIG_WRITE_WORD(MEAR1, mear1);
+ CONFIG_WRITE_WORD(EMEAR1, emear1);
+ CONFIG_WRITE_WORD(MSAR2, msar2);
+ CONFIG_WRITE_WORD(EMSAR2, emsar2);
+ CONFIG_WRITE_WORD(MEAR2, mear2);
+ CONFIG_WRITE_WORD(EMEAR2, emear2);
+ CONFIG_WRITE_BYTE(MBER, mber);
+
+ return (1 << (col + row + 3) ) * bank * m;
}
/*
int misc_init_r(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
/* Write ethernet addr in NVRAM for VxWorks */
- nvram_write(CFG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
+ nvram_write(CONFIG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
(char*)&gd->bd->bi_enetaddr[0], 6);
return 0;
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}