board_f: Drop return value from initdram()

[people/ms/u-boot.git] / board / freescale / ls1043aqds / ls1043aqds.c

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index d6696ca8120abd80051a78391e8c35f47f5f071d..538bba53da9997de5ed53c4dd9102232d1f1b8ea 100644 (file)
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -11,13 +11,13 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/fdt.h>
+#include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
 #include <ahci.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <scsi.h>
 #include <fm_eth.h>
-#include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
 #include <spl.h>
@@ -40,6 +40,9 @@ enum {
 #define CFG_SD_MUX3_MUX4       0x1 /* MUX4 */
 #define CFG_SD_MUX4_SLOT3      0x0 /* SLOT3 TX/RX1 */
 #define CFG_SD_MUX4_SLOT1      0x1 /* SLOT1 TX/RX3 */
+#define CFG_UART_MUX_MASK      0x6
+#define CFG_UART_MUX_SHIFT     1
+#define CFG_LPUART_EN          0x1
 
 int checkboard(void)
 {
@@ -62,8 +65,8 @@ int checkboard(void)
                puts("PromJet\n");
        else if (sw == 0x9)
                puts("NAND\n");
-       else if (sw == 0x15)
-               printf("IFCCard\n");
+       else if (sw == 0xF)
+               printf("QSPI\n");
        else
                printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
 #endif
@@ -150,7 +153,11 @@ int dram_init(void)
         * before accessing DDR SPD.
         */
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
-       gd->ram_size = initdram(0);
+       initdram();
+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+       /* This will break-before-make MMU for DDR */
+       update_early_mmu_table();
+#endif
 
        return 0;
 }
@@ -165,8 +172,7 @@ void board_retimer_init(void)
        u8 reg;
 
        /* Retimer is connected to I2C1_CH7_CH5 */
-       reg = I2C_MUX_CH7;
-       i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
+       select_i2c_ch_pca9547(I2C_MUX_CH7);
        reg = I2C_MUX_CH5;
        i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
 
@@ -214,12 +220,44 @@ void board_retimer_init(void)
        i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
        reg = 0xcd;
        i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
+
+       /* Return the default channel */
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 }
 
 int board_early_init_f(void)
 {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       u32 usb_pwrfault;
+#endif
+#ifdef CONFIG_LPUART
+       u8 uart;
+#endif
+
+#ifdef CONFIG_SYS_I2C_EARLY_INIT
+       i2c_early_init_f();
+#endif
        fsl_lsch2_early_init_f();
 
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+       out_be32(&scfg->rcwpmuxcr0, 0x3333);
+       out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+       usb_pwrfault =
+               (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+               (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+               (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
+       out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+
+#ifdef CONFIG_LPUART
+       /* We use lpuart0 as system console */
+       uart = QIXIS_READ(brdcfg[14]);
+       uart &= ~CFG_UART_MUX_MASK;
+       uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
+       QIXIS_WRITE(brdcfg[14], uart);
+#endif
+
        return 0;
 }
 
@@ -275,13 +313,9 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-                                  CONFIG_SYS_CCI400_ADDR;
-
-       /* Set CCI-400 control override register to enable barrier
-        * transaction */
-       out_le32(&cci->ctrl_ord,
-                CCI400_CTRLORD_EN_BARRIER);
+#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
+       erratum_a010315();
+#endif
 
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        board_retimer_init();
@@ -290,25 +324,38 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
-#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
-       enable_layerscape_ns_access();
-#endif
-
-#ifdef CONFIG_ENV_IS_NOWHERE
-       gd->env_addr = (ulong)&default_environment[0];
-#endif
        return 0;
 }
 
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+       u64 base[CONFIG_NR_DRAM_BANKS];
+       u64 size[CONFIG_NR_DRAM_BANKS];
+       u8 reg;
+
+       /* fixup DT for the two DDR banks */
+       base[0] = gd->bd->bi_dram[0].start;
+       size[0] = gd->bd->bi_dram[0].size;
+       base[1] = gd->bd->bi_dram[1].start;
+       size[1] = gd->bd->bi_dram[1].size;
+
+       fdt_fixup_memory_banks(blob, base, size, 2);
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
        fdt_fixup_fman_ethernet(blob);
        fdt_fixup_board_enet(blob);
 #endif
+
+       reg = QIXIS_READ(brdcfg[0]);
+       reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+       /* Disable IFC if QSPI is enabled */
+       if (reg == 0xF)
+               do_fixup_by_compat(blob, "fsl,ifc",
+                                  "status", "disabled", 8 + 1, 1);
+
        return 0;
 }
 #endif