armv8: LS2080A: Rename LS2085A to reflect LS2080A

[people/ms/u-boot.git] / board / freescale / ls2080aqds / ddr.c

diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2080aqds/ddr.c
similarity index 98%
rename from board/freescale/ls2085ardb/ddr.c
rename to board/freescale/ls2080aqds/ddr.c
index 8d71ae12646a0594466857c709d1ecbe9961cf21..ae681de35eb785ee4f6b352112dab9703bf47467 100644 (file)
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
 {
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
        u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+#endif
        const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
        ulong ddr_freq;
        int slot;
@@ -79,7 +81,7 @@ found:
                pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
                pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
                pbsp->wrlvl_ctl_3);
-
+#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
        if (ctrl_num == CONFIG_DP_DDR_CTRL) {
                /* force DDR bus width to 32 bits */
                popts->data_bus_width = 1;
@@ -114,6 +116,7 @@ found:
                pdimm[slot].dq_mapping[16] = 0;
                pdimm[slot].dq_mapping[17] = 0;
        }
+#endif
        /* To work at higher than 1333MT/s */
        popts->half_strength_driver_enable = 0;
        /*