armv8: LS2080A: Rename LS2085A to reflect LS2080A

[people/ms/u-boot.git] / board / freescale / ls2080ardb / README

diff --git a/board/freescale/ls2085ardb/README b/board/freescale/ls2080ardb/README
similarity index 94%
rename from board/freescale/ls2085ardb/README
rename to board/freescale/ls2080ardb/README
index 2f18243a8b2dbb8d11846d84802e3ed808a39698..7fc2569648173499798f40e79162b590d211a286 100644 (file)
--- a/board/freescale/ls2085ardb/README
+++ b/board/freescale/ls2080ardb/README
@@ -1,17 +1,17 @@
 Overview
 --------
-The LS2085A Reference Design (RDB) is a high-performance computing,
-evaluation, and development platform that supports the QorIQ LS2085A
+The LS2080A Reference Design (RDB) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
-LS2085A SoC Overview
+LS2080A SoC Overview
 ------------------
-The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
 processor cores with high-performance data path acceleration logic and network
 and peripheral bus interfaces required for networking, telecom/datacom,
 wireless infrastructure, and mil/aerospace applications.
 
-The LS2085A SoC includes the following function and features:
+The LS2080A SoC includes the following function and features:
 
  - Eight 64-bit ARM Cortex-A57 CPUs
  - 1 MB platform cache with ECC
@@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features:
  - Service processor (SP) provides pre-boot initialization and secure-boot
   capabilities
 
- LS2085ARDB board Overview
+ LS2080ARDB board Overview
  -----------------------
  - SERDES Connections, 16 lanes supporting:
       - PCI Express - 3.0