/*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
- * CREDITS: Kim Phillips contribute to LIBFDT code
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
#include <spd_sdram.h>
-#if defined(CONFIG_OF_LIBFDT)
+#include <tsec.h>
#include <libfdt.h>
-#endif
-#if defined(CONFIG_PQ_MDS_PIB)
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <fsl_mdio.h>
+#include <phy.h>
+#include "pci.h"
#include "../common/pq-mds-pib.h"
-#endif
+
+DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
switch (PARTID_NO_E(spridr)) {
case SPR_8377:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
case SPR_8378:
- fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
+ FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
break;
case SPR_8379:
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
- FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+ FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
break;
default:
printf("serdes not configured: unknown CPU part number: "
- "%04x\n", spridr >> 16);
+ "%04x\n", spridr >> 16);
break;
}
#endif /* CONFIG_FSL_SERDES */
return 0;
}
+#ifdef CONFIG_FSL_ESDHC
+int board_mmc_init(bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
+ bcsr[0xc] |= 0x4c;
+
+ /* Set proper bits in SICR to allow SD signals through */
+ clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
+ clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
+ SICRH_GPIO2_E_SD | SICRH_SPI_SD);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+#endif
+
+#if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
+int board_eth_init(bd_t *bd)
+{
+ struct fsl_pq_mdio_info mdio_info;
+ struct tsec_info_struct tsec_info[2];
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u32 rcwh = in_be32(&im->reset.rcwh);
+ u32 tsec_mode;
+ int num = 0;
+
+ /* New line after Net: */
+ printf("\n");
+
+#ifdef CONFIG_TSEC1
+ SET_STD_TSEC_INFO(tsec_info[num], 1);
+
+ printf(CONFIG_TSEC1_NAME ": ");
+
+ tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+ if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
+ printf("RGMII\n");
+ /* this is default, no need to fixup */
+ } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
+ printf("SGMII\n");
+ tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
+ tsec_info[num].flags = TSEC_GIGABIT;
+ } else {
+ printf("unsupported PHY type\n");
+ }
+ num++;
+#endif
+#ifdef CONFIG_TSEC2
+ SET_STD_TSEC_INFO(tsec_info[num], 2);
+
+ printf(CONFIG_TSEC2_NAME ": ");
+
+ tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+ if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
+ printf("RGMII\n");
+ /* this is default, no need to fixup */
+ } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
+ printf("SGMII\n");
+ tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
+ tsec_info[num].flags = TSEC_GIGABIT;
+ } else {
+ printf("unsupported PHY type\n");
+ }
+ num++;
+#endif
+
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bd, &mdio_info);
+
+ return tsec_eth_init(bd, tsec_info, num);
+}
+
+static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
+ int phy_addr)
+{
+ const u32 *ph;
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, alias);
+ if (off < 0) {
+ printf("WARNING: could not find %s alias: %s.\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
+
+ if (err) {
+ printf("WARNING: could not set phy-connection-type for %s: "
+ "%s.\n", alias, fdt_strerror(err));
+ return;
+ }
+
+ ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
+ if (!ph) {
+ printf("WARNING: could not get phy-handle for %s.\n",
+ alias);
+ return;
+ }
+
+ off = fdt_node_offset_by_phandle(blob, *ph);
+ if (off < 0) {
+ printf("WARNING: could not get phy node for %s: %s\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ phy_addr = cpu_to_fdt32(phy_addr);
+ err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
+ if (err < 0) {
+ printf("WARNING: could not set phy node's reg for %s: "
+ "%s.\n", alias, fdt_strerror(err));
+ return;
+ }
+}
+
+static void ft_tsec_fixup(void *blob, bd_t *bd)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ u32 rcwh = in_be32(&im->reset.rcwh);
+ u32 tsec_mode;
+
+#ifdef CONFIG_TSEC1
+ tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
+ if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
+ __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
+#endif
+
+#ifdef CONFIG_TSEC2
+ tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
+ if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
+ __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
+#endif
+}
+#else
+static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
+#endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
+
int board_early_init_r(void)
{
#ifdef CONFIG_PQ_MDS_PIB
return 0;
}
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
int fixed_sdram(void);
-phys_size_t initdram(int board_type)
+int initdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
+ return -ENXIO;
#if defined(CONFIG_SPD_EEPROM)
msize = spd_sdram();
msize = fixed_sdram();
#endif
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/* Initialize DDR ECC byte */
ddr_enable_ecc(msize * 1024 * 1024);
#endif
/* return total bus DDR size(bytes) */
- return (msize * 1024 * 1024);
+ gd->ram_size = msize * 1024 * 1024;
+
+ return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
return 0;
}
+#ifdef CONFIG_PCI
+int board_pci_host_broken(void)
+{
+ struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
+ const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
+
+ /* It's always OK in case of external arbiter. */
+ if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
+ return 0;
+
+ if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
+ return 1;
+
+ return 0;
+}
+
+static void ft_pci_fixup(void *blob, bd_t *bd)
+{
+ const char *status = "broken (no arbiter)";
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, "pci0");
+ if (off < 0) {
+ printf("WARNING: could not find pci0 alias: %s.\n",
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+ if (err) {
+ printf("WARNING: could not set status for pci0: %s.\n",
+ fdt_strerror(err));
+ return;
+ }
+}
+#endif
+
#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+ ft_tsec_fixup(blob, bd);
+ fsl_fdt_fixup_dr_usb(blob, bd);
+ fdt_fixup_esdhc(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
+ if (board_pci_host_broken())
+ ft_pci_fixup(blob, bd);
+ ft_pcie_fixup(blob, bd);
#endif
+
+ return 0;
}
#endif /* CONFIG_OF_BOARD_SETUP */
projects / people / ms / u-boot.git / blobdiff