/*
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007,2009 Freescale Semiconductor, Inc.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <spd_sdram.h>
#include <i2c.h>
sys_info_t sysinfo;
get_sys_info(&sysinfo);
- clkdiv = (lbc->lcrr & 0x0f) * 2;
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
gur->lbiuiplldcr1 = 0x00078080;
* MPC8568 uses "new" 15-16 style addressing.
*/
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
-extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
-extern void fsl_pci_init(struct pci_controller *hose);
-
-int first_free_busno = 0;
-
/*
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
*/
}
#ifdef CONFIG_PCI
-void
-pci_init_board(void)
+void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
-#ifdef CONFIG_PCI1
-{
- pib_init();
+ struct fsl_pci_info pci_info[2];
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
- struct pci_controller *hose = &pci1_hose;
- struct pci_region *r = hose->regions;
+ int pcie_ep, pcie_configured;
- uint pci_32 = 1; /* PORDEVSR[15] */
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
- uint pci_speed = 66666000;
-
- if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+#ifdef CONFIG_PCI1
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ SET_STD_PCI_INFO(pci_info[num], 1);
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
- pci_arb ? "arbiter" : "external-arbiter"
- );
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_MEM_BASE,
- CONFIG_SYS_PCI1_MEM_PHYS,
- CONFIG_SYS_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCI1_IO_BASE,
- CONFIG_SYS_PCI1_IO_PHYS,
- CONFIG_SYS_PCI1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno = first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- first_free_busno = hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+ pci_arb ? "arbiter" : "external-arbiter",
+ pci_info[num].regs);
+
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf (" PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
#ifdef CONFIG_PCIE1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
- struct pci_region *r = hose->regions;
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
- int pcie_configured = io_sel >= 1;
-
- if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE connected to slot as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
-
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* inbound */
- r += fsl_pci_setup_inbound_windows(r);
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_MEM_BASE,
- CONFIG_SYS_PCIE1_MEM_PHYS,
- CONFIG_SYS_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE1_IO_BASE,
- CONFIG_SYS_PCIE1_IO_PHYS,
- CONFIG_SYS_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
-
- first_free_busno=hose->last_busno+1;
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ SET_STD_PCIE_INFO(pci_info[num], 1);
+ pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+ printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
+ pcie_ep ? "End Point" : "Root Complex",
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie1_hose, first_free_busno);
} else {
- printf (" PCIE: disabled\n");
+ printf (" PCIE1: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
#endif
}
#endif /* CONFIG_PCI */
#if defined(CONFIG_OF_BOARD_SETUP)
-extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
- struct pci_controller *hose);
-
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
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