powerpc: mpc85xx: Fix static TLB table for SDRAM

[people/ms/u-boot.git] / board / freescale / p1022ds / tlb.c

diff --git a/board/freescale/p1022ds/tlb.c b/board/freescale/p1022ds/tlb.c
index e6201127a934d9ecefe9be7e5edb342dacd2eb22..69d5e449e0d46253e42cfa0017f6ca16ab14be19 100644 (file)
--- a/board/freescale/p1022ds/tlb.c
+++ b/board/freescale/p1022ds/tlb.c
@@ -3,10 +3,7 @@
  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
  *          Timur Tabi <timur@freescale.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -41,6 +38,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 1, BOOKE_PAGESZ_1M, 1),
 
+#ifndef CONFIG_SPL_BUILD
        /* W**G* - Flash/promjet, localbus */
        /* This will be changed to *I*G* after relocation to RAM. */
        SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
@@ -67,10 +65,38 @@ struct fsl_e_tlb_entry tlb_table[] = {
        SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
 
        SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_4K, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) || \
+       (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
+       /* **** - eSDHC/eSPI/NAND boot */
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+                     0, 8, BOOKE_PAGESZ_1G, 1),
+       /* **** - eSDHC/eSPI/NAND boot - second 1GB of memory */
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                     CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+                     0, 9, BOOKE_PAGESZ_1G, 1),
+#endif
+
+#ifdef CONFIG_SYS_NAND_BASE
+       /* *I*G - NAND */
+       SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     0, 10, BOOKE_PAGESZ_16K, 1),
+#endif
+
+#ifdef CONFIG_SYS_INIT_L2_ADDR
+       /* *I*G - L2SRAM */
+       SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+                     0, 11, BOOKE_PAGESZ_256K, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);