board_f: Drop return value from initdram()

[people/ms/u-boot.git] / board / freescale / t104xrdb / ddr.c

diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 8f58dd6832ab87f04f47840bbd59208b995ddd43..b99ab953977b634e1ddd57a16a7dce15126f2474 100644 (file)
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -8,28 +8,14 @@
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-               unsigned int controller_number,
-               unsigned int dimm_number)
-{
-       const char dimm_model[] = "RAW timing DDR";
-
-       if ((controller_number == 0) && (dimm_number == 0)) {
-               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-       }
-
-       return 0;
-}
-
 void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)
@@ -46,7 +32,7 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
        pbsp = udimms[0];
 
-       /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+       /* Get clk_adjust according to the board ddr
         * freqency and n_banks specified in board_specific_parameters table.
         */
        ddr_freq = get_ddr_freq(0) / 1000000;
@@ -54,14 +40,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                if (pbsp->n_ranks == pdimm->n_ranks &&
                    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
-                               popts->cpo_override = pbsp->cpo;
-                               popts->write_data_delay =
-                                       pbsp->write_data_delay;
                                popts->clk_adjust = pbsp->clk_adjust;
                                popts->wrlvl_start = pbsp->wrlvl_start;
                                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-                               popts->twot_en = pbsp->force_2t;
                                goto found;
                        }
                        pbsp_highest = pbsp;
@@ -74,13 +56,10 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                printf("for data rate %lu MT/s\n", ddr_freq);
                printf("Trying to use the highest speed (%u) parameters\n",
                       pbsp_highest->datarate_mhz_high);
-               popts->cpo_override = pbsp_highest->cpo;
-               popts->write_data_delay = pbsp_highest->write_data_delay;
                popts->clk_adjust = pbsp_highest->clk_adjust;
                popts->wrlvl_start = pbsp_highest->wrlvl_start;
                popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
                popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
-               popts->twot_en = pbsp_highest->force_2t;
        } else {
                panic("DIMM is not supported by this board");
        }
@@ -96,7 +75,13 @@ found:
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed
         */
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->half_strength_driver_enable = 1;
+       /* optimize cpo for erratum A-009942 */
+       popts->cpo_sample = 0x59;
+#else
        popts->half_strength_driver_enable = 0;
+#endif
        /*
         * Write leveling override
         */
@@ -112,21 +97,47 @@ found:
        popts->zq_en = 1;
 
        /* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+               DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
+}
+
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+       void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+       /* does not provide HW signals for power management */
+       clrbits_8(cpld_base + 0x17, 0x40);
+       /* Disable MCKE isolation */
+       gpio_set_value(2, 0);
+       udelay(1);
 }
+#endif
 
-phys_size_t initdram(int board_type)
+int initdram(void)
 {
        phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
        puts("Initializing....using SPD\n");
-
        dram_size = fsl_ddr_sdram();
-
+#else
+       dram_size =  fsl_ddr_sdram_size();
+#endif
        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
        dram_size *= 0x100000;
 
-       puts("    DDR: ");
-       return dram_size;
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+       fsl_dp_resume();
+#endif
+
+       gd->ram_size = dram_size;
+
+       return 0;
 }