imx8m*_venice: move venice to OF_UPSTREAM

[thirdparty/u-boot.git] / board / gateworks / venice / venice.c

diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index e6fa7eb3d73f561b0d6974bfd6e1e6b9830e39b1..f54f1186b68674bdfb2aa6de1a49737d54720508 100644 (file)
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -6,9 +6,12 @@
 #include <fdt_support.h>
 #include <init.h>
 #include <led.h>
+#include <mmc.h>
 #include <miiphy.h>
+#include <mmc.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
 
 #include "eeprom.h"
 
@@ -17,17 +20,18 @@ int board_phys_sdram_size(phys_size_t *size)
        if (!size)
                return -EINVAL;
 
-       *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+       *size = get_ram_size((void *)PHYS_SDRAM, (long)PHYS_SDRAM_SIZE + (long)PHYS_SDRAM_2_SIZE);
 
        return 0;
 }
 
-int board_fit_config_name_match(const char *name)
+int board_fit_config_name_match(const char *path)
 {
-       int i  = 0;
-       const char *dtb;
+       const char *name = path + strlen("freescale/");
        static char init;
+       const char *dtb;
        char buf[32];
+       int i  = 0;
 
        do {
                dtb = eeprom_get_dtb_name(i++, buf, sizeof(buf));
@@ -57,24 +61,10 @@ static int __maybe_unused setup_fec(void)
        return 0;
 }
 
-static int __maybe_unused setup_eqos(void)
-{
-       struct iomuxc_gpr_base_regs *gpr =
-               (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
-       /* set INTF as RGMII, enable RGMII TXC clock */
-       clrsetbits_le32(&gpr->gpr[1],
-                       IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
-       setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
-
-       return set_clk_eqos(ENET_125MHZ);
-}
-
 #if (IS_ENABLED(CONFIG_NET))
 int board_phy_config(struct phy_device *phydev)
 {
        unsigned short val;
-       ofnode node;
 
        switch (phydev->phy_id) {
        case 0x2000a231: /* TI DP83867 GbE PHY */
@@ -85,21 +75,6 @@ int board_phy_config(struct phy_device *phydev)
                val |= 0xb << 8; /* LED2(Green;Link/Act): blink for TX/RX act */
                phy_write(phydev, MDIO_DEVAD_NONE, 24, val);
                break;
-       case 0xd565a401: /* MaxLinear GPY111 */
-               puts("GPY111 ");
-               node = phy_get_ofnode(phydev);
-               if (ofnode_valid(node)) {
-                       u32 rx_delay, tx_delay;
-
-                       rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000);
-                       tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000);
-                       val = phy_read(phydev, MDIO_DEVAD_NONE, 0x17);
-                       val &= ~((0x7 << 12) | (0x7 << 8));
-                       val |= (rx_delay / 500) << 12;
-                       val |= (tx_delay / 500) << 8;
-                       phy_write(phydev, MDIO_DEVAD_NONE, 0x17, val);
-               }
-               break;
        }
 
        if (phydev->drv->config)
@@ -115,8 +90,6 @@ int board_init(void)
 
        if (IS_ENABLED(CONFIG_FEC_MXC))
                setup_fec();
-       if (IS_ENABLED(CONFIG_DWC_ETH_QOS))
-               setup_eqos();
 
        return 0;
 }
@@ -124,10 +97,12 @@ int board_init(void)
 int board_late_init(void)
 {
        const char *str;
+       struct mmc *mmc = NULL;
        char env[32];
        int ret, i;
        u8 enetaddr[6];
        char fdt[64];
+       int bootdev;
 
        /* Set board serial/model */
        if (!env_get("serial#"))
@@ -162,6 +137,74 @@ int board_late_init(void)
                i++;
        } while (!ret);
 
+       /*
+        * set bootdev/bootblk/bootpart (used in firmware_update script)
+        * dynamically depending on boot device and SoC
+        */
+       bootdev = -1;
+       switch (get_boot_device()) {
+       case SD1_BOOT:
+       case MMC1_BOOT: /* SDHC1 */
+               bootdev = 0;
+               break;
+       case SD2_BOOT:
+       case MMC2_BOOT: /* SDHC2 */
+               bootdev = 1;
+               break;
+       case SD3_BOOT:
+       case MMC3_BOOT: /* SDHC3 */
+               bootdev = 2;
+               break;
+       default:
+               bootdev = 2; /* assume SDHC3 (eMMC) if booting over SDP */
+               break;
+       }
+       if (bootdev != -1)
+               mmc = find_mmc_device(bootdev);
+       if (mmc) {
+               int bootblk;
+
+               if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
+                       bootblk = 32 * SZ_1K / 512;
+               else
+                       bootblk = 33 * SZ_1K / 512;
+               mmc_init(mmc);
+               if (!IS_SD(mmc)) {
+                       int bootpart;
+
+                       switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+                       case 1: /* boot0 */
+                               bootpart = 1;
+                               break;
+                       case 2: /* boot1 */
+                               bootpart = 2;
+                               break;
+                       case 7: /* user */
+                       default:
+                               bootpart = 0;
+                               break;
+                       }
+                       /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot parts */
+                       if ((IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP)) &&
+                           (bootpart == 1 || bootpart == 2))
+                               bootblk = 0;
+                       env_set_hex("bootpart", bootpart);
+                       env_set_hex("bootblk", bootblk);
+               } else { /* SD */
+                       env_set("bootpart", "");
+                       env_set_hex("bootblk", bootblk);
+               }
+               env_set_hex("dev", bootdev);
+       }
+
+       /* override soc=imx8m to provide a more specific soc name */
+       if (IS_ENABLED(CONFIG_IMX8MN))
+               env_set("soc", "imx8mn");
+       else if (IS_ENABLED(CONFIG_IMX8MP))
+               env_set("soc", "imx8mp");
+       else if (IS_ENABLED(CONFIG_IMX8MM))
+               env_set("soc", "imx8mm");
+
        return 0;
 }
 
@@ -170,6 +213,20 @@ int board_mmc_get_env_dev(int devno)
        return devno;
 }
 
+uint mmc_get_env_part(struct mmc *mmc)
+{
+       if (!IS_SD(mmc)) {
+               switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+               case 1:
+                       return 1;
+               case 2:
+                       return 2;
+               }
+       }
+
+       return 0;
+}
+
 int ft_board_setup(void *fdt, struct bd_info *bd)
 {
        const char *base_model = eeprom_get_baseboard_model();
@@ -182,12 +239,12 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
        if (!strncmp(base_model, "GW73", 4)) {
                pcbrev = get_pcb_rev(base_model);
 
-               if (pcbrev > 'B') {
+               if (pcbrev > 'B' && pcbrev < 'E') {
                        printf("adjusting dt for %s\n", base_model);
 
                        /*
-                        * revC replaced PCIe 5-port switch with 4-port
-                        * which changed ethernet1 PCIe GbE
+                        * revC/D/E has PCIe 4-port switch which changes
+                        * ethernet1 PCIe GbE:
                         * from: pcie@0,0/pcie@1,0/pcie@2,4/pcie@6.0
                         *   to: pcie@0,0/pcie@1,0/pcie@2,3/pcie@5.0
                         */