/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2008-2009
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
+ *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#include <mpc5xxx.h>
#include <pci.h>
-#if defined(CONFIG_MPC5200_DDR)
+#if defined(CONFIG_DDR_MT46V16M16)
#include "mt46v16m16-75.h"
-#else
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
#include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
#endif
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
- hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
__asm__ volatile ("sync");
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
#if SDRAM_DDR
#endif
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
- hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
__asm__ volatile ("sync");
/* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
- hi_addr_bit;
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
__asm__ volatile ("sync");
/* set mode register */
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
- ulong test1, test2;
+#ifndef CONFIG_SYS_RAMBOOT
+ long test1, test2;
/* setup SDRAM chip selects */
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
/* find RAM size using SDRAM CS0 only */
sdram_start(0);
- test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
sdram_start(1);
- test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x20000000);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start(0);
dramsize = test1;
}
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
} else {
dramsize = 0;
}
+#endif /* CONFIG_SYS_RAMBOOT */
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CFG_RAMBOOT */
-
-/* return dramsize + dramsize2; */
return dramsize;
}
*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}
-#ifdef CONFIG_PCI
+int misc_init_r (void) {
+ extern int inkadiag_init_r (void);
+
+ /*
+ * The command table used for the subcommands of inkadiag
+ * needs to be relocated manually.
+ */
+ return inkadiag_init_r();
+}
+
+int misc_init_f (void)
+{
+ char tmp[10];
+ int i, br;
+
+ i = getenv_r("brightness", tmp, sizeof(tmp));
+ br = (i > 0)
+ ? (int) simple_strtoul (tmp, NULL, 10)
+ : CONFIG_SYS_BRIGHTNESS;
+ if (br > 255)
+ br = 255;
+
+ /* Initialize GPIO output pins.
+ */
+ /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
+ *(vu_long *)MPC5XXX_GPT0_ENABLE =
+ *(vu_long *)MPC5XXX_GPT1_ENABLE =
+ *(vu_long *)MPC5XXX_GPT2_ENABLE =
+ *(vu_long *)MPC5XXX_GPT3_ENABLE =
+ *(vu_long *)MPC5XXX_GPT4_ENABLE =
+ *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
+
+ /* Configure GPT7 as PWM timer, 1kHz, no ints. */
+ *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
+ *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
+ *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
+ *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
+
+ /* Configure PSC3_6,7 as GPIO output */
+ *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
+ *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
+
+ /* Configure PSC3_8 as GPIO output, no interrupt */
+ *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
+ *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
+ *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
+
+ /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+ *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
+ *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
+
+ /* Set LR mirror bit because it is low-active */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
+ /*
+ * Reset Coral-P graphics controller
+ */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
+ return 0;
+}
+
+#ifdef CONFIG_PCI
static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void)
{
- pci_mpc5xxx_init(&hose);
+ pci_mpc5xxx_init(&hose);
}
#endif
+#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ /* Deassert reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ /* Make a delay. MPC5200 spec says 25 usec min */
+ udelay(500000);
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ }
+}
+#endif
projects / people / ms / u-boot.git / blobdiff