*/
0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
*/
0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
0xFFFFEC05, /* last */
- _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
- * This is no UPM entry point. The following definition uses
- * the remaining space to establish an initialization
- * sequence, which is executed by a RUN command.
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
*
*/
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
udelay(1000);
/*
- * RESET is implemented by a positive pulse of at least 1 us
- * at the reset pin.
+ * RESET is implemented by a positive pulse of at least 1 us
+ * at the reset pin.
*
* Configure RESET pins for NS DP83843 PHY, and RESET chip.
*