rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / board / netstal / hcu5 / sdram.c

diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 6b1b53a4d058bb62d08d583fe94e8a3555e3ec8e..f59bd7d1895fa6a2f07d4267cdfa14c31e02500b 100644 (file)
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -40,28 +40,6 @@
 void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 
-#define DDR_DCR_BASE 0x10
-#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
-#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */
-
-#define DDR0_01_INT_MASK_MASK             0x000000FF
-#define DDR0_00_INT_ACK_ALL               0x7F000000
-#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
-#define DDR0_01_INT_MASK_ALL_OFF          0x00000000
-
-#define DDR0_17_DLLLOCKREG_MASK           0x00010000 /* Read only */
-#define DDR0_17_DLLLOCKREG_UNLOCKED       0x00000000
-#define DDR0_17_DLLLOCKREG_LOCKED         0x00010000
-
-#define DDR0_22                         0x16
-/* ECC */
-#define DDR0_22_CTRL_RAW_MASK             0x03000000
-#define DDR0_22_CTRL_RAW_ECC_DISABLE      0x00000000 /* ECC not enabled */
-#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY   0x01000000 /* ECC no correction */
-#define DDR0_22_CTRL_RAW_NO_ECC_RAM       0x02000000 /* Not a ECC RAM*/
-#define DDR0_22_CTRL_RAW_ECC_ENABLE       0x03000000 /* ECC correcting on */
-#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
-
 #define ECC_RAM                                0x03267F0B
 #define NO_ECC_RAM                     0x00267F0B
 
@@ -93,7 +71,7 @@ void board_add_ram_info(int use_default)
        }
 
        get_sys_info(&board_cfg);
-       printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+       printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
 
        mfsdram(DDR0_03, val);
        val = DDR0_03_CASLAT_DECODE(val);
@@ -111,11 +89,11 @@ static int wait_for_dlllock(void)
        /* -----------------------------------------------------------+
         * Wait for the DCC master delay line to finish calibration
         * ----------------------------------------------------------*/
-       mtdcr(ddrcfga, DDR0_17);
+       mtdcr(memcfga, DDR0_17);
        val = DDR0_17_DLLLOCKREG_UNLOCKED;
 
        while (wait != 0xffff) {
-               val = mfdcr(ddrcfgd);
+               val = mfdcr(memcfgd);
                if ((val & DDR0_17_DLLLOCKREG_MASK) ==
                    DDR0_17_DLLLOCKREG_LOCKED)
                        /* dlllockreg bit on */
@@ -144,7 +122,7 @@ void sdram_panic(const char *reason)
 }
 
 #ifdef CONFIG_DDR_ECC
-static void blank_string(int size)
+void blank_string(int size)
 {
        int i;
 
@@ -221,7 +199,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
        unsigned int dram_size = 0;
 
@@ -285,20 +263,20 @@ long int initdram (int board_type)
        /*
         * Program tlb entries for this size (dynamic)
         */
-       remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+       remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
        program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
 
        /*
         * Setup 2nd TLB with same physical address but different virtual
         * address with cache enabled. This is done for fast ECC generation.
         */
-       program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+       program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
 
 #ifdef CONFIG_DDR_ECC
        /*
         * If ECC is enabled, initialize the parity bits.
         */
-       program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+       program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
 #endif
 
        return (dram_size);