rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / board / netstal / hcu5 / sdram.c

diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index d8817b831af0b51178756f1744ae41dd3daa0986..f59bd7d1895fa6a2f07d4267cdfa14c31e02500b 100644 (file)
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -71,7 +71,7 @@ void board_add_ram_info(int use_default)
        }
 
        get_sys_info(&board_cfg);
-       printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+       printf(", %lu MHz", (board_cfg.freqPLB * 2) / 1000000);
 
        mfsdram(DDR0_03, val);
        val = DDR0_03_CASLAT_DECODE(val);
@@ -122,7 +122,7 @@ void sdram_panic(const char *reason)
 }
 
 #ifdef CONFIG_DDR_ECC
-static void blank_string(int size)
+void blank_string(int size)
 {
        int i;
 
@@ -199,7 +199,7 @@ static void program_ecc(unsigned long start_address, unsigned long num_bytes)
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
        unsigned int dram_size = 0;
 
@@ -263,20 +263,20 @@ long int initdram (int board_type)
        /*
         * Program tlb entries for this size (dynamic)
         */
-       remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+       remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
        program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
 
        /*
         * Setup 2nd TLB with same physical address but different virtual
         * address with cache enabled. This is done for fast ECC generation.
         */
-       program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+       program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
 
 #ifdef CONFIG_DDR_ECC
        /*
         * If ECC is enabled, initialize the parity bits.
         */
-       program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+       program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
 #endif
 
        return (dram_size);