#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_86xx.h>
-#include <spd.h>
-
-#if defined(CONFIG_OF_FLAT_TREE)
-#include <ft_build.h>
-extern void ft_cpu_setup (void *blob, bd_t * bd);
-#endif
+#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <libfdt.h>
+#include <fdt_support.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc (unsigned int dram_size);
#endif
-#if defined(CONFIG_SPD_EEPROM)
-#include "spd_sdram.h"
-#endif
-
-void sdram_init (void);
long int fixed_sdram (void);
int board_early_init_f (void)
{
puts ("Board: Wind River SBC8641D\n");
-#ifdef CONFIG_PCI
-
- volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
- volatile ccsr_gur_t *gur = &immap->im_gur;
- volatile ccsr_pex_t *pex1 = &immap->im_pex1;
-
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
- uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
- uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
-
- if ((io_sel == 2 || io_sel == 3 || io_sel == 5
- || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
- && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
- debug ("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
- debug ("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det);
- if (pex1->pme_msg_det) {
- pex1->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",
- pex1->pme_msg_det);
- }
- debug ("\n");
- } else {
- puts ("PCI-EXPRESS 1: Disabled in hardware\n");
- }
-
-#else
- puts ("PCI-EXPRESS1: Disabled in configuration\n");
-#endif
-
return 0;
}
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
{
long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram ();
+ dram_size = fsl_ddr_sdram();
#else
dram_size = fixed_sdram ();
#endif
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
puts (" DDR: ");
return dram_size;
#endif
return dram_size;
}
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
- uint *pstart = (uint *) CFG_MEMTEST_START;
- uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+ uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
puts ("SDRAM test phase 1:\n");
*/
long int fixed_sdram (void)
{
-#if !defined(CFG_RAMBOOT)
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
- ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
- ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
- ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
- ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
- ddr->cs0_config = CFG_DDR_CS0_CONFIG;
- ddr->cs1_config = CFG_DDR_CS1_CONFIG;
- ddr->cs2_config = CFG_DDR_CS2_CONFIG;
- ddr->cs3_config = CFG_DDR_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
- ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
- ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
- ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
- ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
- ddr->sdram_mode_1 = CFG_DDR_MODE_1;
- ddr->sdram_mode_2 = CFG_DDR_MODE_2;
- ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
- ddr->sdram_interval = CFG_DDR_INTERVAL;
- ddr->sdram_data_init = CFG_DDR_DATA_INIT;
- ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+ ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+ ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
+ ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+ ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+ ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
+ ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+ ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
+ ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+ ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+ ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
asm ("sync;isync");
udelay (500);
- ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
+ ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
asm ("sync; isync");
udelay (500);
ddr = &immap->im_ddr2;
- ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
- ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
- ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
- ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
- ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
- ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
- ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
- ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
- ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
- ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
- ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
- ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
- ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
- ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
- ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
- ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
- ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
- ddr->sdram_interval = CFG_DDR2_INTERVAL;
- ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
- ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
+ ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
+ ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
+ ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
+ ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
+ ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
+ ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
+ ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
+ ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
+ ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
+ ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
+ ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
+ ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
+ ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+ ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
+ ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+ ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
+ ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+ ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
+ ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
+ ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
asm ("sync;isync");
udelay (500);
- ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
+ ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
asm ("sync; isync");
udelay (500);
#endif
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif /* !defined(CONFIG_SPD_EEPROM) */
};
#endif
-static struct pci_controller hose = {
+static struct pci_controller pci1_hose = {
#ifndef CONFIG_PCI_PNP
- config_table:pci_mpc86xxcts_config_table,
+ config_table:pci_mpc86xxcts_config_table
#endif
};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+int first_free_busno = 0;
-#endif /* CONFIG_PCI */
+void pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
+ >> MPC8641_PORDEVSR_IO_SEL_SHIFT;
-void pci_init_board (void)
+#ifdef CONFIG_PCI1
{
-#ifdef CONFIG_PCI
- extern void pci_mpc86xx_init (struct pci_controller *hose);
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+#ifdef DEBUG
+ uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
+ >> MPC8641_PORBMSR_HA_SHIFT;
+ uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
+#endif
+ if ((io_sel == 2 || io_sel == 3 || io_sel == 5
+ || io_sel == 6 || io_sel == 7 || io_sel == 0xF)
+ && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
+ debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
+ debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug(" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ debug("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CONFIG_SYS_PCI1_MEM_BASE,
+ CONFIG_SYS_PCI1_MEM_PHYS,
+ CONFIG_SYS_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CONFIG_SYS_PCI1_IO_BASE,
+ CONFIG_SYS_PCI1_IO_PHYS,
+ CONFIG_SYS_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
- pci_mpc86xx_init (&hose);
-#endif /* CONFIG_PCI */
+ } else {
+ puts("PCI-EXPRESS 1: Disabled\n");
+ }
}
+#else
+ puts("PCI-EXPRESS1: Disabled\n");
+#endif /* CONFIG_PCI1 */
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup (void *blob, bd_t * bd)
+#ifdef CONFIG_PCI2
{
- u32 *p;
- int len;
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci2_hose;
+
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCI_MEMORY_BUS,
+ CONFIG_SYS_PCI_MEMORY_PHYS,
+ CONFIG_SYS_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CONFIG_SYS_PCI2_MEM_BASE,
+ CONFIG_SYS_PCI2_MEM_PHYS,
+ CONFIG_SYS_PCI2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CONFIG_SYS_PCI2_IO_BASE,
+ CONFIG_SYS_PCI2_IO_PHYS,
+ CONFIG_SYS_PCI2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+}
+#else
+ puts("PCI-EXPRESS 2: Disabled\n");
+#endif /* CONFIG_PCI2 */
+
+}
- ft_cpu_setup (blob, bd);
- p = ft_get_prop (blob, "/memory/reg", &len);
- if (p != NULL) {
- *p++ = cpu_to_be32 (bd->bi_memstart);
- *p = cpu_to_be32 (bd->bi_memsize);
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup (void *blob, bd_t *bd)
+{
+ int node, tmp[2];
+ const char *path;
+
+ ft_cpu_setup(blob, bd);
+
+ node = fdt_path_offset(blob, "/aliases");
+ tmp[0] = 0;
+ if (node >= 0) {
+#ifdef CONFIG_PCI1
+ path = fdt_getprop(blob, node, "pci0", NULL);
+ if (path) {
+ tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
+#ifdef CONFIG_PCI2
+ path = fdt_getprop(blob, node, "pci1", NULL);
+ if (path) {
+ tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
+ do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
+ }
+#endif
}
}
#endif
projects / people / ms / u-boot.git / blobdiff