#include <malloc.h>
#include <nand.h>
#include <asm/io.h>
+#include "axs10x.h"
+
+DECLARE_GLOBAL_DATA_PTR;
#define BUS_WIDTH 8 /* AXI data bus width in bytes */
uint32_t buffer_ptr1; /* DES3 */
};
-#define NAND_REG_WRITE(r, v) writel(v, CONFIG_SYS_NAND_BASE + r)
-#define NAND_REG_READ(r) readl(CONFIG_SYS_NAND_BASE + r)
+#define NAND_REG_WRITE(r, v) \
+ writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
+#define NAND_REG_READ(r) \
+ readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
static struct nand_bd *bd; /* DMA buffer descriptors */
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
writel(0, &bd->buffer_ptr1);
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)bd,
+ (unsigned long)bd + sizeof(struct nand_bd));
+
/* Issue "write" command */
NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
writel(0, &bd->buffer_ptr1);
+ /* Flush modified buffer descriptor */
+ flush_dcache_range((unsigned long)bd,
+ (unsigned long)bd + sizeof(struct nand_bd));
+
/* Issue "read" command */
NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
nand->write_buf = axs101_nand_write_buf;
nand->read_buf = axs101_nand_read_buf;
+ /* MBv3 has NAND IC with 16-bit data bus */
+ if (gd->board_type == AXS_MB_V3)
+ nand->options |= NAND_BUSWIDTH_16;
+
return 0;
}